[PATCH] D31124: AMDGPU/SI: Add lane tracking to SI Scheduler

[Axel Davy via Phabricator via llvm-commits]

axeldavy added inline comments.


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Comment at: lib/Target/AMDGPU/SIMachineScheduler.cpp:1388
+        // Reset read - undef flags and update them later.
+        for (auto &Op : MI.operands())
+          if (Op.isReg() && Op.isDef())
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vpykhtin wrote:
> duplicated code
This is duplicated with your iterative scheduler, and I suggested to have a common function for both schedulers and the default scheduler (you said you extracted the code from there), but you didn't take the comment into account.
Do you want a common function for both SI schedulers or with default scheduler too ?


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Comment at: lib/Target/AMDGPU/SIMachineScheduler.h:498
 
-  std::set<unsigned> getInRegs() {
-    std::set<unsigned> InRegs;
-    for (const auto &RegMaskPair : RPTracker.getPressure().LiveInRegs) {
-      InRegs.insert(RegMaskPair.RegUnit);
-    }
-    return InRegs;
+  const SmallVector<RegisterMaskPair, 8> getInRegs() {
+    return RPTracker.getPressure().LiveInRegs;
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vpykhtin wrote:
> You can make it const and return reference, like
> 
> const SmallVector<RegisterMaskPair, 8> &getInRegs() const;
Right.

I had in mind we'd add the correct computation of the block liveins here (as for GCNScheduler), but for now we can return reference.


Repository:
  rL LLVM

https://reviews.llvm.org/D31124