[PATCH] D31124: AMDGPU/SI: Add lane tracking to SI Scheduler

[Valery Pykhtin via Phabricator via llvm-commits]

vpykhtin added a comment.

Ok, I understood  SIScheduleBlockCreator::scheduleInsideBlocks() moves instructions to actually get LiveIn and LiveOut set for a block, but this is rather heavy. Have you thought about getting those using DAG directly, not regpressure tracker? By the common sence the dependencies between blocks correspond to that liveness info. There is a problem however: LiveIn and LiveOut dependencies aren't modelled for boundary SUs. I have local patch that build such dependencies - scheduling region LiveIns edges comes from EntrySU, LiveOut - to ExitSU. Another problem - dependency edges doesn't have lanemask, need to think how to deal with this.



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Comment at: lib/Target/AMDGPU/SIMachineScheduler.cpp:387
+      LIS->getInstructionIndex(*EndBlock).getRegSlot(), MRI,
+      LIS);
+    // Being in LaneMask but not in RegMaskPair.LaneMask means the lane
----------------
I would move  LIS->getInstructionIndex(*BeginBlock).getRegSlot(), LIS->getInstructionIndex(*EndBlock).getRegSlot() out of the loop


Repository:
  rL LLVM

https://reviews.llvm.org/D31124