[PATCH] D31400: DAG: Fix mis-legalization of i1 zextload

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In https://reviews.llvm.org/D31400#711522, @arsenm wrote:

> In https://reviews.llvm.org/D31400#711506, @efriedma wrote:
>
> > Can you describe the issue you're trying to fix here in a bit more detail?  As far as I know, the bits are in fact guaranteed to be zero.
>
>
> i1 zextload to i32 is being legalized to AssertZext (zextload i8 to i32), so there was no and truncating to a single bit. As far as I know nothing is guaranteed about the high bits in memory of a < byte value.


If an <N x i1> vector is supposed to be packed in memory, I would expect 
%cast.ptr = bitcast <64 x i1> to i1*
%elt0 = load i1, i1* %cast.ptr 
to do the right thing and truncate the value


https://reviews.llvm.org/D31400