[PATCH] D31400: DAG: Fix mis-legalization of i1 zextload

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In https://reviews.llvm.org/D31400#711506, @efriedma wrote:

> Can you describe the issue you're trying to fix here in a bit more detail?  As far as I know, the bits are in fact guaranteed to be zero.


i1 zextload to i32 is being legalized to AssertZext (zextload i8 to i32), so there was no and truncating to a single bit. As far as I know nothing is guaranteed about the high bits in memory of a < byte value.


https://reviews.llvm.org/D31400