[PATCH] D31403: [SDAG] Deal with deleted node in PromoteIntShiftOp

[Nirav Dave via Phabricator via llvm-commits]

niravd created this revision.

Deal with case that initial node is deleted during dag-combine leading
to an assertional failure in promoteIntShiftOp.

Fixes PR32420.


https://reviews.llvm.org/D31403

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/X86/pr32420.ll


Index: test/CodeGen/X86/pr32420.ll
===================================================================
--- /dev/null
+++ test/CodeGen/X86/pr32420.ll
@@ -0,0 +1,49 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.12.0"
+
+%struct.S = type { i16, [2 x i8] }
+
+ at a = common local_unnamed_addr global %struct.S zeroinitializer, align 4
+ at b = common local_unnamed_addr global i32 0, align 4
+ at c = common local_unnamed_addr global i8 0, align 1
+
+define i32 @PR32420(i1 %lnot) {
+; CHECK-LABEL: PR32420:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    movq _a@{{.*}}(%rip), %rax
+; CHECK-NEXT:    movzwl (%rax), %eax
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shll $12, %ecx
+; CHECK-NEXT:    sarw $12, %cx
+; CHECK-NEXT:    movq _c@{{.*}}(%rip), %rdx
+; CHECK-NEXT:    movb (%rdx), %dl
+; CHECK-NEXT:    orb %cl, %dl
+; CHECK-NEXT:    movsbl %dl, %edx
+; CHECK-NEXT:    movswl %cx, %ecx
+; CHECK-NEXT:    andl %edx, %ecx
+; CHECK-NEXT:    movq _b@{{.*}}(%rip), %rdx
+; CHECK-NEXT:    movl %ecx, (%rdx)
+; CHECK-NEXT:    andl %edi, %eax
+; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    retq
+  %cast = zext i1 %lnot to i32
+  %load2 = load i16, i16* getelementptr inbounds (%struct.S, %struct.S* @a, i64 0, i32 0), align 4
+  %shl3 = shl i16 %load2, 12
+  %ashr4 = ashr i16 %shl3, 12
+  %cast527 = trunc i16 %ashr4 to i8
+  %t2 = load volatile i8, i8* @c, align 1
+  %or = or i8 %t2, %cast527
+  %conv8 = sext i8 %or to i32
+  %load9 = load i16, i16* getelementptr inbounds (%struct.S, %struct.S* @a, i64 0, i32 0), align 4
+  %shl10 = shl i16 %load9, 12
+  %ashr11 = ashr i16 %shl10, 12
+  %cast12 = sext i16 %ashr11 to i32
+  %and = and i32 %conv8, %cast12
+  store i32 %and, i32* @b, align 4
+  %cast1629 = zext i16 %load9 to i32
+  %and21 = and i32 %cast1629, %cast
+  ret i32 %and21
+}
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1145,26 +1145,32 @@
   if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
     assert(PVT != VT && "Don't know what type to promote to!");
 
+    DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG));
+
     bool Replace = false;
     SDValue N0 = Op.getOperand(0);
+    SDValue N1 = Op.getOperand(1);
     if (Opc == ISD::SRA)
-      N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
+      N0 = SExtPromoteOperand(N0, PVT);
     else if (Opc == ISD::SRL)
-      N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
+      N0 = ZExtPromoteOperand(N0, PVT);
     else
       N0 = PromoteOperand(N0, PVT, Replace);
+
     if (!N0.getNode())
       return SDValue();
 
-    AddToWorklist(N0.getNode());
-    if (Replace)
+    SDLoc DL(Op);
+    SDValue RV =
+        DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, N0, N1));
+    if (Replace) {
+      AddToWorklist(N0.getNode());
       ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
+    }
 
-    DEBUG(dbgs() << "\nPromoting ";
-          Op.getNode()->dump(&DAG));
-    SDLoc DL(Op);
-    return DAG.getNode(ISD::TRUNCATE, DL, VT,
-                       DAG.getNode(Opc, DL, PVT, N0, Op.getOperand(1)));
+    // Deal with Op being deleted.
+    if (Op.getNode() && Op.getOpcode() != ISD::DELETED_NODE)
+      return RV;
   }
   return SDValue();
 }


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