[llvm] r298806 - [X86][SSE] Add computeKnownBitsForTargetNode support for (V)PSLL/(V)PSRL instructions

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sun Mar 26 08:17:55 2017
New Revision: 298806

URL: http://llvm.org/viewvc/llvm-project?rev=298806&view=rev
Log:
[X86][SSE] Add computeKnownBitsForTargetNode support for (V)PSLL/(V)PSRL instructions

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/combine-abs.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=298806&r1=298805&r2=298806&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Mar 26 08:17:55 2017
@@ -26591,6 +26591,7 @@ void X86TargetLowering::computeKnownBits
                                                       unsigned Depth) const {
   unsigned BitWidth = KnownZero.getBitWidth();
   unsigned Opc = Op.getOpcode();
+  EVT VT = Op.getValueType();
   assert((Opc >= ISD::BUILTIN_OP_END ||
           Opc == ISD::INTRINSIC_WO_CHAIN ||
           Opc == ISD::INTRINSIC_W_CHAIN ||
@@ -26624,9 +26625,33 @@ void X86TargetLowering::computeKnownBits
     KnownZero.setBits(NumLoBits, BitWidth);
     break;
   }
+  case X86ISD::VSHLI:
+  case X86ISD::VSRLI: {
+    if (auto *ShiftImm = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+      if (ShiftImm->getAPIntValue().uge(VT.getScalarSizeInBits())) {
+        KnownZero = APInt::getAllOnesValue(BitWidth);
+        break;
+      }
+
+      DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth + 1);
+      unsigned ShAmt = ShiftImm->getZExtValue();
+      if (Opc == X86ISD::VSHLI) {
+        KnownZero = KnownZero << ShAmt;
+        KnownOne = KnownOne << ShAmt;
+        // Low bits are known zero.
+        KnownZero.setLowBits(ShAmt);
+      } else {
+        KnownZero = KnownZero.lshr(ShAmt);
+        KnownOne = KnownOne.lshr(ShAmt);
+        // High bits are known zero.
+        KnownZero.setHighBits(ShAmt);
+      }
+    }
+    break;
+  }
   case X86ISD::VZEXT: {
     SDValue N0 = Op.getOperand(0);
-    unsigned NumElts = Op.getValueType().getVectorNumElements();
+    unsigned NumElts = VT.getVectorNumElements();
 
     EVT SrcVT = N0.getValueType();
     unsigned InNumElts = SrcVT.getVectorNumElements();

Modified: llvm/trunk/test/CodeGen/X86/combine-abs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-abs.ll?rev=298806&r1=298805&r2=298806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-abs.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-abs.ll Sun Mar 26 08:17:55 2017
@@ -84,7 +84,6 @@ define <8 x i32> @combine_v8i32_abs_pos(
 ; CHECK-LABEL: combine_v8i32_abs_pos:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    vpsrld $1, %ymm0, %ymm0
-; CHECK-NEXT:    vpabsd %ymm0, %ymm0
 ; CHECK-NEXT:    retq
   %1 = lshr <8 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
   %2 = call <8 x i32> @llvm.x86.avx2.pabs.d(<8 x i32> %1)