[llvm] r298780 - [X86][SSE] Added ComputeNumSignBitsForTargetNode support for (V)PSRAI
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 25 12:58:36 PDT 2017
Author: rksimon
Date: Sat Mar 25 14:58:36 2017
New Revision: 298780
URL: http://llvm.org/viewvc/llvm-project?rev=298780&view=rev
Log:
[X86][SSE] Added ComputeNumSignBitsForTargetNode support for (V)PSRAI
Part 2 of 3.
Differential Revision: https://reviews.llvm.org/D31347
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/combine-and.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=298780&r1=298779&r2=298780&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Mar 25 14:58:36 2017
@@ -26661,6 +26661,15 @@ unsigned X86TargetLowering::ComputeNumSi
return Tmp;
}
+ case X86ISD::VSRAI: {
+ SDValue Src = Op.getOperand(0);
+ unsigned Tmp = DAG.ComputeNumSignBits(Src, Depth + 1);
+ unsigned VTBits = Op.getValueType().getScalarSizeInBits();
+ APInt ShiftVal = cast<ConstantSDNode>(Op.getOperand(1))->getAPIntValue();
+ ShiftVal += Tmp;
+ return ShiftVal.uge(VTBits) ? VTBits : ShiftVal.getZExtValue();
+ }
+
case X86ISD::PCMPGT:
case X86ISD::PCMPEQ:
case X86ISD::CMPP:
Modified: llvm/trunk/test/CodeGen/X86/combine-and.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-and.ll?rev=298780&r1=298779&r2=298780&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-and.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-and.ll Sat Mar 25 14:58:36 2017
@@ -254,7 +254,7 @@ define <8 x i16> @ashr_mask1_v8i16(<8 x
; CHECK-LABEL: ashr_mask1_v8i16:
; CHECK: # BB#0:
; CHECK-NEXT: psraw $15, %xmm0
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-NEXT: psrlw $15, %xmm0
; CHECK-NEXT: retq
%1 = ashr <8 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
%2 = and <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -265,7 +265,7 @@ define <4 x i32> @ashr_mask7_v4i32(<4 x
; CHECK-LABEL: ashr_mask7_v4i32:
; CHECK: # BB#0:
; CHECK-NEXT: psrad $31, %xmm0
-; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-NEXT: psrld $29, %xmm0
; CHECK-NEXT: retq
%1 = ashr <4 x i32> %a0, <i32 31, i32 31, i32 31, i32 31>
%2 = and <4 x i32> %1, <i32 7, i32 7, i32 7, i32 7>
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