[PATCH] D31239: [WIP] Add Caching of Known Bits in InstCombine

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Mar 24 15:33:14 PDT 2017


craig.topper added a comment.

I'm seeing more problems than just nsw/nuw flags here.

sext.ll test is failing because SimplifyDemandedInstructions bits determined that this

%and = and i32 %x, 16

  shl i32 %and, 27

Simplified to just the shl because we were only demanding the MSB of the shift. This occurred after we had cached the known bits for the shl as having 31 lsbs as 0. But without the "and" in there we can no longer guarantee the lower bits of the shift result are 0.

I also got a failure on shift.ll not reported here. This was caused by getShiftedValue rewriting operands and changing constants of other shifts. This effectively shifts the Known bits and thus the cache needs to be invalidate.


https://reviews.llvm.org/D31239





More information about the llvm-commits mailing list