[llvm] r298716 - [X86][SSE] Add ashr + mask test cases.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Fri Mar 24 12:25:47 2017
New Revision: 298716

URL: http://llvm.org/viewvc/llvm-project?rev=298716&view=rev
Log:
[X86][SSE] Add ashr + mask test cases.

Test cases showing cases where we're missing an opportunity to lshr a value with an extended sign to avoid loading a mask

Modified:
    llvm/trunk/test/CodeGen/X86/combine-and.ll

Modified: llvm/trunk/test/CodeGen/X86/combine-and.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-and.ll?rev=298716&r1=298715&r2=298716&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-and.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-and.ll Fri Mar 24 12:25:47 2017
@@ -245,3 +245,29 @@ define <4 x i32> @and_or_zext_v4i16(<4 x
   %3 = and <4 x i32> %2, <i32 65536, i32 65536, i32 65536, i32 65536>
   ret <4 x i32> %3
 }
+
+;
+; known sign bits folding
+;
+
+define <8 x i16> @ashr_mask1_v8i16(<8 x i16> %a0) {
+; CHECK-LABEL: ashr_mask1_v8i16:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    psraw $15, %xmm0
+; CHECK-NEXT:    pand {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %1 = ashr <8 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+  %2 = and <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %2
+}
+
+define <4 x i32> @ashr_mask7_v4i32(<4 x i32> %a0) {
+; CHECK-LABEL: ashr_mask7_v4i32:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    psrad $31, %xmm0
+; CHECK-NEXT:    pand {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %1 = ashr <4 x i32> %a0, <i32 31, i32 31, i32 31, i32 31>
+  %2 = and <4 x i32> %1, <i32 7, i32 7, i32 7, i32 7>
+  ret <4 x i32> %2
+}