[PATCH] D31311: [DAGCombiner] Add vector demanded elements support to ComputeNumSignBits

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
Herald added subscribers: nhaehnle, arsenm.

Currently ComputeNumSignBits returns the minimum number of sign bits for all elements of vector data, when we may only be interested in one/some of the elements.

This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original ComputeNumSignBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1.

I've only added support for a few opcodes so far (the ones that have proven straightforward to test), all others will default to demanding all elements but can be updated in due course.

Followup to https://reviews.llvm.org/D25691.


Repository:
  rL LLVM

https://reviews.llvm.org/D31311

Files:
  include/llvm/CodeGen/SelectionDAG.h
  include/llvm/Target/TargetLowering.h
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  lib/CodeGen/SelectionDAG/TargetLowering.cpp
  lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  lib/Target/AMDGPU/AMDGPUISelLowering.h
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86ISelLowering.h
  test/CodeGen/X86/known-bits-vector.ll

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