[PATCH] D31265: Fix computeKnownBits for ARMISD::CMOV
Pirama Arumuga Nainar via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 23 09:58:59 PDT 2017
pirama updated this revision to Diff 92827.
pirama added a comment.
Added '[ARM]' to commit message.
https://reviews.llvm.org/D31265
Files:
lib/Target/ARM/ARMISelLowering.cpp
test/CodeGen/ARM/no-cmov2bfi.ll
Index: test/CodeGen/ARM/no-cmov2bfi.ll
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/no-cmov2bfi.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -mtriple=thumbv7 | FileCheck --check-prefix=CHECK-NOBFI %s
+
+declare zeroext i1 @dummy()
+
+define i8 @test(i8 %a1, i1 %c) {
+; CHECK-NOBFI-NOT: bfi
+; CHECK-NOBFI: bl dummy
+; CHECK-NOBFI: cmp r0, #0
+; CHECK-NOBFI: it ne
+; CHECK-NOBFI: orrne [[REG:r[0-9]+]], [[REG]], #8
+; CHECK-NOBFI: mov r0, [[REG]]
+
+ %1 = and i8 %a1, -9
+ %2 = select i1 %c, i8 %1, i8 %a1
+ %3 = tail call zeroext i1 @dummy()
+ %4 = or i8 %2, 8
+ %ret = select i1 %3, i8 %4, i8 %2
+ ret i8 %ret
+}
Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -11628,8 +11628,8 @@
if (Op.getOpcode() == ARMISD::CMOV) {
APInt KZ2(KnownZero.getBitWidth(), 0);
APInt KO2(KnownOne.getBitWidth(), 0);
- computeKnownBits(DAG, Op.getOperand(1), KnownZero, KnownOne);
- computeKnownBits(DAG, Op.getOperand(2), KZ2, KO2);
+ computeKnownBits(DAG, Op.getOperand(0), KnownZero, KnownOne);
+ computeKnownBits(DAG, Op.getOperand(1), KZ2, KO2);
KnownZero &= KZ2;
KnownOne &= KO2;
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