[llvm] r298590 - [GlobalISel][X86] clang-format. NFC

[Igor Breger via llvm-commits]

Author: ibreger
Date: Thu Mar 23 07:13:29 2017
New Revision: 298590

URL: http://llvm.org/viewvc/llvm-project?rev=298590&view=rev
Log:
[GlobalISel][X86] clang-format. NFC

Modified:
    llvm/trunk/lib/Target/X86/X86CallLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
    llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp
    llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp
    llvm/trunk/lib/Target/X86/X86RegisterBankInfo.h

Modified: llvm/trunk/lib/Target/X86/X86CallLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallLowering.cpp?rev=298590&r1=298589&r2=298590&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CallLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CallLowering.cpp Thu Mar 23 07:13:29 2017
@@ -14,14 +14,14 @@
 //===----------------------------------------------------------------------===//
 
 #include "X86CallLowering.h"
+#include "X86CallingConv.h"
 #include "X86ISelLowering.h"
 #include "X86InstrInfo.h"
 #include "X86TargetMachine.h"
-#include "X86CallingConv.h"
 
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
-#include "llvm/CodeGen/MachineValueType.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MachineValueType.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
 
 using namespace llvm;
@@ -116,7 +116,7 @@ bool X86CallLowering::lowerReturn(Machin
                       });
 
     FuncReturnHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
-    if(!handleAssignments(MIRBuilder, SplitArgs, Handler))
+    if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
       return false;
   }
 
@@ -137,9 +137,8 @@ struct FormalArgHandler : public CallLow
     int FI = MFI.CreateFixedObject(Size, Offset, true);
     MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
 
-    unsigned AddrReg =
-        MRI.createGenericVirtualRegister(LLT::pointer(0,
-                                         DL.getPointerSizeInBits(0)));
+    unsigned AddrReg = MRI.createGenericVirtualRegister(
+        LLT::pointer(0, DL.getPointerSizeInBits(0)));
     MIRBuilder.buildFrameIndex(AddrReg, FI);
     return AddrReg;
   }
@@ -161,7 +160,7 @@ struct FormalArgHandler : public CallLow
 
   const DataLayout &DL;
 };
-}
+} // namespace
 
 bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
                                            const Function &F,
@@ -169,7 +168,7 @@ bool X86CallLowering::lowerFormalArgumen
   if (F.arg_empty())
     return true;
 
-  //TODO: handle variadic function
+  // TODO: handle variadic function
   if (F.isVarArg())
     return false;
 
@@ -203,7 +202,7 @@ bool X86CallLowering::lowerFormalArgumen
 
   MachineBasicBlock &MBB = MIRBuilder.getMBB();
   if (!MBB.empty())
-     MIRBuilder.setInstr(*MBB.begin());
+    MIRBuilder.setInstr(*MBB.begin());
 
   FormalArgHandler Handler(MIRBuilder, MRI, CC_X86, DL);
   if (!handleAssignments(MIRBuilder, SplitArgs, Handler))

Modified: llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp?rev=298590&r1=298589&r2=298590&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp Thu Mar 23 07:13:29 2017
@@ -118,13 +118,13 @@ static bool selectCopy(MachineInstr &I,
   // No need to constrain SrcReg. It will get constrained when
   // we hit another of its use or its defs.
   // Copies do not have constraints.
-  const TargetRegisterClass *OldRC  = MRI.getRegClassOrNull(DstReg);
+  const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg);
   if (!OldRC || !RC->hasSubClassEq(OldRC)) {
     if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
-        DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
-                     << " operand\n");
-        return false;
-      }
+      DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
+                   << " operand\n");
+      return false;
+    }
   }
   I.setDesc(TII.get(X86::COPY));
   return true;
@@ -152,7 +152,8 @@ bool X86InstructionSelector::select(Mach
   assert(I.getNumOperands() == I.getNumExplicitOperands() &&
          "Generic instruction has unexpected implicit operands\n");
 
-  // TODO: This should be implemented by tblgen, pattern with predicate not supported yet.
+  // TODO: This should be implemented by tblgen, pattern with predicate not
+  // supported yet.
   if (selectBinaryOp(I, MRI))
     return true;
 
@@ -300,4 +301,3 @@ bool X86InstructionSelector::selectBinar
 
   return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
 }
-

Modified: llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp?rev=298590&r1=298589&r2=298590&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp Thu Mar 23 07:13:29 2017
@@ -85,5 +85,4 @@ void X86LegalizerInfo::setLegalizerInfoS
   for (unsigned BinOp : {G_ADD, G_SUB})
     for (auto Ty : {v4s32})
       setAction({BinOp, Ty}, Legal);
-
 }

Modified: llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp?rev=298590&r1=298589&r2=298590&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp Thu Mar 23 07:13:29 2017
@@ -72,8 +72,7 @@ X86RegisterBankInfo::getOperandsMapping(
   unsigned NumOperands = MI.getNumOperands();
   LLT Ty = MRI.getType(MI.getOperand(0).getReg());
 
-  if (NumOperands != 3 ||
-      (Ty != MRI.getType(MI.getOperand(1).getReg())) ||
+  if (NumOperands != 3 || (Ty != MRI.getType(MI.getOperand(1).getReg())) ||
       (Ty != MRI.getType(MI.getOperand(2).getReg())))
     llvm_unreachable("Unsupported operand maping yet.");
 
@@ -106,7 +105,7 @@ X86RegisterBankInfo::getOperandsMapping(
         ValMapIdx = VMI_3OpsFp64Idx;
         break;
       default:
-          llvm_unreachable("Unsupported register size.");
+        llvm_unreachable("Unsupported register size.");
       }
     }
   } else {

Modified: llvm/trunk/lib/Target/X86/X86RegisterBankInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterBankInfo.h?rev=298590&r1=298589&r2=298590&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterBankInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterBankInfo.h Thu Mar 23 07:13:29 2017
@@ -50,5 +50,5 @@ public:
   InstructionMapping getInstrMapping(const MachineInstr &MI) const override;
 };
 
-} // End llvm namespace.
+} // namespace llvm
 #endif