[PATCH] D30941: Better testing of schedule model instruction latencies/throughputs

[Andrew V. Tischenko via Phabricator via llvm-commits]

avt77 added a comment.

In https://reviews.llvm.org/D30941#707504, @hfinkel wrote:

> In https://reviews.llvm.org/D30941#707464, @avt77 wrote:
>
> > I did everything accordingly to Hal's requirements except one: the default value of "print-schedule" switch is false because otherewise we have "Unexpected Failures: 530" and it's X86 tests ony. The problem is very simple: update_llc_test_checks.py generates CHECKs like here
> >
> > ; XOP-AVX1-NEXT:    vextractf128 $1, %ymm2, %xmm5
>
>
> I did not realize that CHECK-NEXT always matched the whole line. That's interesting.


If you'd like to CHECK the prefix only you should use something like

CHECK:    vextractf128 $1, %ymm2, %xmm5**{{*}}**

> In any case, if this is an update_llc_test_checks.py problem, why don't you use it to update the tests?

I can use it to update the tests but it means I should update 530 tests. Is it acceptable? Should I do it? For me it is not a problem but is it OK for review?


https://reviews.llvm.org/D30941