[llvm] r298484 - [SystemZ] Don't drop any operands in expandZExtPseudo()
Jonas Paulsson via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 21 23:03:32 PDT 2017
Author: jonpa
Date: Wed Mar 22 01:03:32 2017
New Revision: 298484
URL: http://llvm.org/viewvc/llvm-project?rev=298484&view=rev
Log:
[SystemZ] Don't drop any operands in expandZExtPseudo()
Make sure that any operands, e.g. of an implicit def of a super reg is
transferred to the new instruction.
Review: Ulrich Weigand
Added:
llvm/trunk/test/CodeGen/SystemZ/expand-zext-pseudo.ll
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=298484&r1=298483&r2=298484&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Wed Mar 22 01:03:32 2017
@@ -23,7 +23,6 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -221,9 +220,15 @@ void SystemZInstrInfo::expandLOCRPseudo(
// are low registers, otherwise use RISB[LH]G.
void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
unsigned Size) const {
- emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
- MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
- Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
+ MachineInstrBuilder MIB =
+ emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
+ MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
+ Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
+
+ // Keep the remaining operands as-is.
+ for (unsigned I = 2; I < MI.getNumOperands(); ++I)
+ MIB.add(MI.getOperand(I));
+
MI.eraseFromParent();
}
@@ -263,12 +268,13 @@ void SystemZInstrInfo::expandLoadStackGu
// are low registers, otherwise use RISB[LH]G. Size is the number of bits
// taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
// KillSrc is true if this move is the last use of SrcReg.
-void SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- const DebugLoc &DL, unsigned DestReg,
- unsigned SrcReg, unsigned LowLowOpcode,
- unsigned Size, bool KillSrc,
- bool UndefSrc) const {
+MachineInstrBuilder
+SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, unsigned DestReg,
+ unsigned SrcReg, unsigned LowLowOpcode,
+ unsigned Size, bool KillSrc,
+ bool UndefSrc) const {
unsigned Opcode;
bool DestIsHigh = isHighReg(DestReg);
bool SrcIsHigh = isHighReg(SrcReg);
@@ -279,12 +285,11 @@ void SystemZInstrInfo::emitGRX32Move(Mac
else if (!DestIsHigh && SrcIsHigh)
Opcode = SystemZ::RISBLH;
else {
- BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
+ return BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
- return;
}
unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
- BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
+ return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
.addReg(DestReg, RegState::Undef)
.addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))
.addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h?rev=298484&r1=298483&r2=298484&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h Wed Mar 22 01:03:32 2017
@@ -19,6 +19,7 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Target/TargetInstrInfo.h"
#include <cstdint>
@@ -160,10 +161,13 @@ class SystemZInstrInfo : public SystemZG
void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
unsigned Size) const;
void expandLoadStackGuard(MachineInstr *MI) const;
- void emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
- unsigned LowLowOpcode, unsigned Size, bool KillSrc,
- bool UndefSrc) const;
+
+ MachineInstrBuilder
+ emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
+ unsigned LowLowOpcode, unsigned Size, bool KillSrc,
+ bool UndefSrc) const;
+
virtual void anchor();
protected:
Added: llvm/trunk/test/CodeGen/SystemZ/expand-zext-pseudo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/expand-zext-pseudo.ll?rev=298484&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/expand-zext-pseudo.ll (added)
+++ llvm/trunk/test/CodeGen/SystemZ/expand-zext-pseudo.ll Wed Mar 22 01:03:32 2017
@@ -0,0 +1,132 @@
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs | FileCheck %s
+;
+; Test that a def operand of super-reg is not dropped during post RA pseudo
+; expansion in expandZExtPseudo().
+
+define void @fun_llvm_stress_reduced(i8*, i32*, i64*, i32) {
+; CHECK: .text
+BB:
+ %A = alloca i32
+ %Sl24 = select i1 undef, i32* %1, i32* %1
+ %L26 = load i16, i16* undef
+ %L32 = load i32, i32* %Sl24
+ br label %CF847
+
+CF847: ; preds = %CF878, %BB
+ %L61 = load i16, i16* undef
+ br label %CF878
+
+CF878: ; preds = %CF847
+ %PC66 = bitcast i32* %Sl24 to double*
+ %Sl67 = select i1 undef, <2 x i32> undef, <2 x i32> undef
+ %Cmp68 = icmp ugt i32 undef, %3
+ br i1 %Cmp68, label %CF847, label %CF863
+
+CF863: ; preds = %CF878
+ %L84 = load i16, i16* undef
+ br label %CF825
+
+CF825: ; preds = %CF825, %CF863
+ %Sl105 = select i1 undef, i1 undef, i1 undef
+ br i1 %Sl105, label %CF825, label %CF856
+
+CF856: ; preds = %CF856, %CF825
+ %Cmp114 = icmp ult i16 -24837, %L61
+ br i1 %Cmp114, label %CF856, label %CF875
+
+CF875: ; preds = %CF856
+ %Shuff124 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> <i32 1, i32 3>
+ %PC126 = bitcast i32* %A to i64*
+ br label %CF827
+
+CF827: ; preds = %CF923, %CF911, %CF875
+ %Sl142 = select i1 undef, i64 undef, i64 -1
+ %B148 = sdiv i32 409071, 409071
+ %E153 = extractelement <2 x i32> %Shuff124, i32 1
+ br label %CF911
+
+CF911: ; preds = %CF827
+ br i1 undef, label %CF827, label %CF867
+
+CF867: ; preds = %CF911
+ br label %CF870
+
+CF870: ; preds = %CF870, %CF867
+ store i8 0, i8* %0
+ %FC176 = fptoui double undef to i1
+ br i1 %FC176, label %CF870, label %CF923
+
+CF923: ; preds = %CF870
+ %L179 = load i16, i16* undef
+ %Sl191 = select i1 undef, i64* %PC126, i64* %PC126
+ br i1 false, label %CF827, label %CF828
+
+CF828: ; preds = %CF905, %CF923
+ %B205 = urem i16 -7553, undef
+ %E209 = extractelement <2 x i32> %Sl67, i32 1
+ %Cmp215 = icmp ugt i16 %L179, 0
+ br label %CF905
+
+CF905: ; preds = %CF828
+ %E231 = extractelement <4 x i1> undef, i32 1
+ br i1 %E231, label %CF828, label %CF829
+
+CF829: ; preds = %CF909, %CF829, %CF905
+ %B234 = udiv i16 %L26, %L84
+ br i1 undef, label %CF829, label %CF894
+
+CF894: ; preds = %CF894, %CF829
+ store i64 %Sl142, i64* %Sl191
+ %Sl241 = select i1 %Cmp114, i1 false, i1 %Cmp215
+ br i1 %Sl241, label %CF894, label %CF907
+
+CF907: ; preds = %CF894
+ %B247 = udiv i32 0, %E153
+ %PC248 = bitcast i64* %2 to i8*
+ br label %CF909
+
+CF909: ; preds = %CF907
+ store i1 %FC176, i1* undef
+ %Cmp263 = icmp ugt i1 undef, %Sl241
+ br i1 %Cmp263, label %CF829, label %CF830
+
+CF830: ; preds = %CF909
+ %B304 = urem i16 %L84, %B205
+ %I311 = insertelement <2 x i32> %Shuff124, i32 %B247, i32 1
+ store i8 0, i8* %0
+ %Sl373 = select i1 %Cmp68, i32 0, i32 %E153
+ br label %CF833
+
+CF833: ; preds = %CF880, %CF830
+ br label %CF880
+
+CF880: ; preds = %CF833
+ %Cmp412 = icmp ne i16 %B234, -18725
+ br i1 %Cmp412, label %CF833, label %CF865
+
+CF865: ; preds = %CF880
+ store double 0.000000e+00, double* %PC66
+ br label %CF860
+
+CF860: ; preds = %CF860, %CF865
+ store i8 0, i8* %PC248
+ %Cmp600 = icmp sge i32 %B148, undef
+ br i1 %Cmp600, label %CF860, label %CF913
+
+CF913: ; preds = %CF860
+ store i32 %E209, i32* undef
+ store i32 %Sl373, i32* undef
+ %Cmp771 = icmp ule i32 undef, %L32
+ br label %CF842
+
+CF842: ; preds = %CF925, %CF913
+ br label %CF925
+
+CF925: ; preds = %CF842
+ %Cmp778 = icmp sgt i1 %Cmp771, %Sl241
+ br i1 %Cmp778, label %CF842, label %CF898
+
+CF898: ; preds = %CF925
+ %Sl785 = select i1 %Cmp600, i16 undef, i16 %B304
+ unreachable
+}
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