[PATCH] D31211: [AMDGPU] Add target feature new-addr
Yaxun Liu via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 21 14:28:36 PDT 2017
yaxunl updated this revision to Diff 92547.
yaxunl added a comment.
Add a test.
https://reviews.llvm.org/D31211
Files:
lib/Target/AMDGPU/AMDGPU.td
lib/Target/AMDGPU/AMDGPUSubtarget.h
lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
test/CodeGen/AMDGPU/new-addr.ll
Index: test/CodeGen/AMDGPU/new-addr.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/new-addr.ll
@@ -0,0 +1,13 @@
+; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mattr=+new-addr -verify-machineinstrs < %s
+; Just check the target feature and data layout is accepted without error.
+
+target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
+target triple = "amdgcn"
+
+; Function Attrs: noinline nounwind
+define void @foo() #0 {
+entry:
+ ret void
+}
+
+attributes #0 = { "target-features"="+new-addr"}
Index: lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -161,7 +161,7 @@
"Run GCN scheduler to maximize occupancy",
createGCNMaxOccupancyMachineScheduler);
-static StringRef computeDataLayout(const Triple &TT) {
+static StringRef computeDataLayout(const Triple &TT, StringRef FS) {
if (TT.getArch() == Triple::r600) {
// 32-bit pointers.
return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
@@ -170,9 +170,13 @@
// 32-bit private, local, and region pointers. 64-bit global, constant and
// flat.
- return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
+ if (FS.find("+new-addr") != StringRef::npos)
+ return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
+ return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
+ "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
+ "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
}
LLVM_READNONE
@@ -199,7 +203,7 @@
Optional<Reloc::Model> RM,
CodeModel::Model CM,
CodeGenOpt::Level OptLevel)
- : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
+ : LLVMTargetMachine(T, computeDataLayout(TT, FS), TT, getGPUOrDefault(TT, CPU),
FS, Options, getEffectiveRelocModel(RM), CM, OptLevel),
TLOF(createTLOF(getTargetTriple())) {
initAsmInfo();
Index: lib/Target/AMDGPU/AMDGPUSubtarget.h
===================================================================
--- lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -117,6 +117,7 @@
bool DebuggerInsertNops;
bool DebuggerReserveRegs;
bool DebuggerEmitPrologue;
+ bool UseNewAddr;
// Used as options.
bool EnableVGPRSpilling;
@@ -345,6 +346,10 @@
return FlatForGlobal;
}
+ bool useNewAddr() const {
+ return UseNewAddr;
+ }
+
bool hasUnalignedBufferAccess() const {
return UnalignedBufferAccess;
}
Index: lib/Target/AMDGPU/AMDGPU.td
===================================================================
--- lib/Target/AMDGPU/AMDGPU.td
+++ lib/Target/AMDGPU/AMDGPU.td
@@ -104,6 +104,12 @@
"VI SGPR initilization bug requiring a fixed SGPR allocation size"
>;
+def FeatureNewAddrSpace : SubtargetFeature<"new-addr",
+ "UseNewAddr",
+ "false",
+ "Use new address space mapping where generic address space is 0"
+>;
+
class SubtargetFeatureFetchLimit <string Value> :
SubtargetFeature <"fetch"#Value,
"TexVTXClauseSize",
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