[PATCH] D31123: RegisterPressure: Add operators to RegisterMaskPair

[Axel Davy via Phabricator via llvm-commits]

axeldavy updated this revision to Diff 92296.

Repository:
  rL LLVM

https://reviews.llvm.org/D31123

Files:
  include/llvm/CodeGen/RegisterPressure.h


Index: include/llvm/CodeGen/RegisterPressure.h
===================================================================
--- include/llvm/CodeGen/RegisterPressure.h
+++ include/llvm/CodeGen/RegisterPressure.h
@@ -41,6 +41,15 @@
 
   RegisterMaskPair(unsigned RegUnit, LaneBitmask LaneMask)
       : RegUnit(RegUnit), LaneMask(LaneMask) {}
+
+  bool operator==(const RegisterMaskPair &RP) const {
+    return RegUnit == RP.RegUnit && LaneMask == RP.LaneMask;
+  }
+
+  bool operator<(const RegisterMaskPair &RP) const {
+    return RegUnit < RP.RegUnit ||
+      (RegUnit == RP.RegUnit && LaneMask < RP.LaneMask);
+  }
 };
 
 /// Base class for register pressure results.


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D31123.92296.patch
Type: text/x-patch
Size: 665 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170319/65ba2265/attachment.bin>