[PATCH] D31081: [ARM] ScheduleDAGRRList::DelayForLiveRegsBottomUp must consider OptionalDefs

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

OptionalDefOperand is only used by the ARM backend, yes.  It's used to avoid creating a bunch of variants of instructions which modify the flag register, CPSR, since almost every arithmetic instruction has an "s" variant.  It's a def of CPSR if the S bit is set, otherwise it's a use of %noreg, or something like that, I think.  This is complicated by the fact that in Thumb1, the non-S variants don't actually exist, which is why we have this particular problem.

Granted, it would be simpler overall to just multiclass the instructions in question, but it would a big project to change that.


Repository:
  rL LLVM

https://reviews.llvm.org/D31081