[llvm] r298103 - [X86] Add SelectionDAG.computeKnownBits test showing inability to handle ISD::ABS

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Fri Mar 17 11:58:15 2017
New Revision: 298103

URL: http://llvm.org/viewvc/llvm-project?rev=298103&view=rev
Log:
[X86] Add SelectionDAG.computeKnownBits test showing inability to handle ISD::ABS

We have to be careful as abs(INT_MIN) == INT_MIN.

Modified:
    llvm/trunk/test/CodeGen/X86/known-bits-vector.ll

Modified: llvm/trunk/test/CodeGen/X86/known-bits-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/known-bits-vector.ll?rev=298103&r1=298102&r2=298103&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/known-bits-vector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/known-bits-vector.ll Fri Mar 17 11:58:15 2017
@@ -555,3 +555,64 @@ define <4 x i32> @knownbits_mask_bitreve
   ret <4 x i32> %3
 }
 declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>) nounwind readnone
+
+; If we don't know that the input isn't INT_MIN we can't combine to sitofp
+define <4 x float> @knownbits_abs_uitofp(<4 x i32> %a0) {
+; X32-LABEL: knownbits_abs_uitofp:
+; X32:       # BB#0:
+; X32-NEXT:    vpabsd %xmm0, %xmm0
+; X32-NEXT:    vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
+; X32-NEXT:    vpsrld $16, %xmm0, %xmm0
+; X32-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
+; X32-NEXT:    vaddps {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-NEXT:    vaddps %xmm0, %xmm1, %xmm0
+; X32-NEXT:    retl
+;
+; X64-LABEL: knownbits_abs_uitofp:
+; X64:       # BB#0:
+; X64-NEXT:    vpabsd %xmm0, %xmm0
+; X64-NEXT:    vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
+; X64-NEXT:    vpsrld $16, %xmm0, %xmm0
+; X64-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
+; X64-NEXT:    vaddps {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT:    vaddps %xmm0, %xmm1, %xmm0
+; X64-NEXT:    retq
+  %1 = sub <4 x i32> zeroinitializer, %a0
+  %2 = icmp slt <4 x i32> %a0, zeroinitializer
+  %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> %a0
+  %4 = uitofp <4 x i32> %3 to <4 x float>
+  ret <4 x float> %4
+}
+
+define <4 x float> @knownbits_or_abs_uitofp(<4 x i32> %a0) {
+; X32-LABEL: knownbits_or_abs_uitofp:
+; X32:       # BB#0:
+; X32-NEXT:    vpor {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
+; X32-NEXT:    vpabsd %xmm0, %xmm0
+; X32-NEXT:    vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
+; X32-NEXT:    vpsrld $16, %xmm0, %xmm0
+; X32-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
+; X32-NEXT:    vaddps {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-NEXT:    vaddps %xmm0, %xmm1, %xmm0
+; X32-NEXT:    retl
+;
+; X64-LABEL: knownbits_or_abs_uitofp:
+; X64:       # BB#0:
+; X64-NEXT:    vpor {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
+; X64-NEXT:    vpabsd %xmm0, %xmm0
+; X64-NEXT:    vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
+; X64-NEXT:    vpsrld $16, %xmm0, %xmm0
+; X64-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
+; X64-NEXT:    vaddps {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT:    vaddps %xmm0, %xmm1, %xmm0
+; X64-NEXT:    retq
+  %1 = or <4 x i32> %a0, <i32 1, i32 0, i32 3, i32 0>
+  %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
+  %3 = sub <4 x i32> zeroinitializer, %2
+  %4 = icmp slt <4 x i32> %2, zeroinitializer
+  %5 = select <4 x i1> %4, <4 x i32> %3, <4 x i32> %2
+  %6 = uitofp <4 x i32> %5 to <4 x float>
+  ret <4 x float> %6
+}