[PATCH] D30744: Improve machine schedulers for in-order processors

[Andrew Trick via Phabricator via llvm-commits]

atrick added a comment.

I just looked at the MachineScheduler implementation. I see this TODO:
`/// TODO: Also check whether the SU must start a new group.`

So, I think your patch is necessary except:

- The SubtargetEmitter can simply set the begin/end group flags for SingleIssue

- Instead of adding an isSingleIssue() API to TargetSchedule, you should add mustBeginGroup() and mustEndGroup() that checks the existing bits in MCSchedClassDesc.

- In the scheduler, mustBeginGroup() is a hazard if CurMOps > 0 when isTop() is true. Similarly, mustEndGroup() is the same hazard for !isTop().

- Your patch needs to handle isTop() && mustEndGroup(); likewise, !isTop() && mustBeginGroup() by calling `bumpCycle(++NextCycle)`. Do this just after setting CurrMOps at ` CurrMOps += IncMOps`, and just before checking the MOps hazard at `while (CurrMOps >= SchedModel->getIssueWidth())`. That obviously needs to be commented: "Bump the cycle count for issue group constraints. This must be done after NextCycle has been adjust for all other stalls. Calling `bumpCycle(X)` with reduces CurrMOps by one issue group and sets `currCycle` to `X`."

Your current implementation of isSingleIssue is actually only half the solution. Implementing the begin/end group bits will make it complete.


https://reviews.llvm.org/D30744