[PATCH] D31081: [ARM] ScheduleDAGRRList::DelayForLiveRegsBottomUp must consider OptionalDefs

[A. Skrobov via Phabricator via llvm-commits]

tyomitch created this revision.
Herald added subscribers: MatzeB, rengolin, aemerson.

https://reviews.llvm.org/D31081

Files:
  lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
  test/CodeGen/Thumb/optionaldef-scheduling.ll


Index: test/CodeGen/Thumb/optionaldef-scheduling.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Thumb/optionaldef-scheduling.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=thumb-eabi %s -verify-machineinstrs -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv6-eabi %s -verify-machineinstrs -o - | FileCheck %s
+
+define i1 @test(i64 %arg) {
+entry:
+  %ispos = icmp sgt i64 %arg, -1
+  %neg = sub i64 0, %arg
+  %sel = select i1 %ispos, i64 %arg, i64 %neg
+  %cmp2 = icmp eq i64 %sel, %arg
+  ret i1 %cmp2
+}
+
+; CHECK: adds
+; CHECK-NOT: eors
+; CHECK: adcs
Index: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1323,6 +1323,14 @@
                                RegAdded, LRegs);
 
     const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
+    if (MCID.hasOptionalDef()) {
+      for (unsigned i = 0; i < MCID.getNumDefs(); ++i)
+        if (MCID.OpInfo[i].isOptionalDef()) {
+          const SDValue &OptionalDef = Node->getOperand(i - Node->getNumValues());
+          unsigned Reg = cast<RegisterSDNode>(OptionalDef)->getReg();
+          CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
+        }
+    }
     if (!MCID.ImplicitDefs)
       continue;
     for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg)


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