[llvm] r297980 - TargetInstrInfo: Provide default implementation of isTailCall().
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 16 13:02:30 PDT 2017
Author: matze
Date: Thu Mar 16 15:02:30 2017
New Revision: 297980
URL: http://llvm.org/viewvc/llvm-project?rev=297980&view=rev
Log:
TargetInstrInfo: Provide default implementation of isTailCall().
In fact this default implementation should be the only implementation,
keep it virtual for now to accomodate targets that don't model flags
correctly.
Differential Revision: https://reviews.llvm.org/D30747
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.h
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=297980&r1=297979&r2=297980&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Thu Mar 16 15:02:30 2017
@@ -1503,9 +1503,11 @@ public:
return None;
}
- /// Determines whether |Inst| is a tail call instruction.
+ /// Determines whether \p Inst is a tail call instruction. Override this
+ /// method on targets that do not properly set MCID::Return and MCID::Call on
+ /// tail call instructions."
virtual bool isTailCall(const MachineInstr &Inst) const {
- return false;
+ return Inst.isReturn() && Inst.isCall();
}
/// True if the instruction is bound to the top of its basic block and no
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=297980&r1=297979&r2=297980&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Thu Mar 16 15:02:30 2017
@@ -1619,17 +1619,6 @@ bool AArch64InstrInfo::isUnscaledLdSt(Ma
return isUnscaledLdSt(MI.getOpcode());
}
-bool AArch64InstrInfo::isTailCall(const MachineInstr &Inst) const
-{
- switch (Inst.getOpcode()) {
- case AArch64::TCRETURNdi:
- case AArch64::TCRETURNri:
- return true;
- default:
- return false;
- }
-}
-
// Is this a candidate for ld/st merging or pairing? For example, we don't
// touch volatiles or load/stores that have a hint to avoid pair formation.
bool AArch64InstrInfo::isCandidateToMergeOrPair(MachineInstr &MI) const {
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h?rev=297980&r1=297979&r2=297980&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h Thu Mar 16 15:02:30 2017
@@ -87,8 +87,6 @@ public:
/// Return true if this is an unscaled load/store.
bool isUnscaledLdSt(MachineInstr &MI) const;
- bool isTailCall(const MachineInstr &Inst) const override;
-
static bool isPairableLdStInst(const MachineInstr &MI) {
switch (MI.getOpcode()) {
default:
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=297980&r1=297979&r2=297980&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Mar 16 15:02:30 2017
@@ -4711,19 +4711,6 @@ bool ARMBaseInstrInfo::hasNOP() const {
return Subtarget.getFeatureBits()[ARM::HasV6KOps];
}
-bool ARMBaseInstrInfo::isTailCall(const MachineInstr &Inst) const
-{
- switch (Inst.getOpcode()) {
- case ARM::TAILJMPd:
- case ARM::TAILJMPr:
- case ARM::TCRETURNdi:
- case ARM::TCRETURNri:
- return true;
- default:
- return false;
- }
-}
-
bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
if (MI->getNumOperands() < 4)
return true;
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=297980&r1=297979&r2=297980&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Thu Mar 16 15:02:30 2017
@@ -109,8 +109,6 @@ public:
getNoopForMachoTarget(NopInst);
}
- bool isTailCall(const MachineInstr &Inst) const override;
-
// Return the non-pre/post incrementing version of 'Opc'. Return 0
// if there is not such an opcode.
virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=297980&r1=297979&r2=297980&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Mar 16 15:02:30 2017
@@ -10177,28 +10177,6 @@ X86InstrInfo::getSerializableDirectMachi
return makeArrayRef(TargetFlags);
}
-bool X86InstrInfo::isTailCall(const MachineInstr &Inst) const {
- switch (Inst.getOpcode()) {
- case X86::TCRETURNdi:
- case X86::TCRETURNmi:
- case X86::TCRETURNri:
- case X86::TCRETURNdi64:
- case X86::TCRETURNmi64:
- case X86::TCRETURNri64:
- case X86::TAILJMPd:
- case X86::TAILJMPm:
- case X86::TAILJMPr:
- case X86::TAILJMPd64:
- case X86::TAILJMPm64:
- case X86::TAILJMPr64:
- case X86::TAILJMPm64_REX:
- case X86::TAILJMPr64_REX:
- return true;
- default:
- return false;
- }
-}
-
namespace {
/// Create Global Base Reg pass. This initializes the PIC
/// global base register for x86-32.
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=297980&r1=297979&r2=297980&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Thu Mar 16 15:02:30 2017
@@ -543,8 +543,6 @@ public:
ArrayRef<std::pair<unsigned, const char *>>
getSerializableDirectMachineOperandTargetFlags() const override;
- bool isTailCall(const MachineInstr &Inst) const override;
-
unsigned getOutliningBenefit(size_t SequenceSize,
size_t Occurrences,
bool CanBeTailCall) const override;
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