[llvm] r297920 - [Hexagon] Updating inline saturate lanes for v62 version.

[Colin LeMahieu via llvm-commits]

Author: colinl
Date: Wed Mar 15 19:35:28 2017
New Revision: 297920

URL: http://llvm.org/viewvc/llvm-project?rev=297920&view=rev
Log:
[Hexagon] Updating inline saturate lanes for v62 version.

Added:
    llvm/trunk/test/MC/Hexagon/bug20416.s
Modified:
    llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp

Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp?rev=297920&r1=297919&r2=297920&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp Wed Mar 15 19:35:28 2017
@@ -105,7 +105,10 @@ void HexagonCVIResource::SetupTUL(TypeUn
   (*TUL)[HexagonII::TypeCVI_VP] = UnitsAndLanes(CVI_XLANE, 1);
   (*TUL)[HexagonII::TypeCVI_VP_VS] = UnitsAndLanes(CVI_XLANE, 2);
   (*TUL)[HexagonII::TypeCVI_VS] = UnitsAndLanes(CVI_SHIFT, 1);
-  (*TUL)[HexagonII::TypeCVI_VINLANESAT] = UnitsAndLanes(CVI_SHIFT, 1);
+  (*TUL)[HexagonII::TypeCVI_VINLANESAT] =
+      (CPU == "hexagonv60" || CPU == "hexagonv61" || CPU == "hexagonv61v1") ?
+      UnitsAndLanes(CVI_SHIFT, 1) :
+      UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
   (*TUL)[HexagonII::TypeCVI_VM_LD] =
       UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
   (*TUL)[HexagonII::TypeCVI_VM_TMP_LD] = UnitsAndLanes(CVI_NONE, 0);

Added: llvm/trunk/test/MC/Hexagon/bug20416.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/bug20416.s?rev=297920&view=auto
==============================================================================
--- llvm/trunk/test/MC/Hexagon/bug20416.s (added)
+++ llvm/trunk/test/MC/Hexagon/bug20416.s Wed Mar 15 19:35:28 2017
@@ -0,0 +1,13 @@
+# RUN: not llvm-mc -mv60 -mhvx -filetype=asm %s 2>%t; FileCheck %s --check-prefix=CHECK-V60-ERROR <%t
+# RUN:     llvm-mc -mv62 -mhvx -filetype=asm %s | FileCheck %s
+
+// for this a v60+/hvx instruction sequence, make sure fails with v60
+// but passes with v62.  this is because this instruction uses different
+// itinerary between v60 and v62
+{
+  v0.h=vsat(v5.w,v9.w)
+  v16.h=vsat(v6.w,v26.w)
+}
+# CHECK-V60-ERROR: rror: invalid instruction packet: slot error
+# CHECK: v0.h = vsat(v5.w,v9.w)
+# CHECK: v16.h = vsat(v6.w,v26.w)