[llvm] r297874 - [GlobalISel][AArch64] Select ADDXri.

[Ahmed Bougacha via llvm-commits]

Author: ab
Date: Wed Mar 15 14:20:59 2017
New Revision: 297874

URL: http://llvm.org/viewvc/llvm-project?rev=297874&view=rev
Log:
[GlobalISel][AArch64] Select ADDXri.

We're now able to select ADDWri thanks to the new complex pattern
support.  Extend that to ADDXri.

Modified:
    llvm/trunk/include/llvm/Target/GlobalISel/Target.td
    llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-binop.mir

Modified: llvm/trunk/include/llvm/Target/GlobalISel/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GlobalISel/Target.td?rev=297874&r1=297873&r2=297874&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/GlobalISel/Target.td (original)
+++ llvm/trunk/include/llvm/Target/GlobalISel/Target.td Wed Mar 15 14:20:59 2017
@@ -22,6 +22,7 @@
 class LLT;
 
 def s32 : LLT;
+def s64 : LLT;
 
 // Defines a matcher for complex operands. This is analogous to ComplexPattern
 // from SelectionDAG.

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=297874&r1=297873&r2=297874&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Wed Mar 15 14:20:59 2017
@@ -693,6 +693,10 @@ def gi_addsub_shifted_imm32 :
     GIComplexOperandMatcher<s32, (ops i32imm, i32imm), "selectArithImmed">,
     GIComplexPatternEquiv<addsub_shifted_imm32>;
 
+def gi_addsub_shifted_imm64 :
+    GIComplexOperandMatcher<s64, (ops i32imm, i32imm), "selectArithImmed">,
+    GIComplexPatternEquiv<addsub_shifted_imm64>;
+
 class neg_addsub_shifted_imm<ValueType Ty>
     : Operand<Ty>, ComplexPattern<Ty, 2, "SelectNegArithImmed", [imm]> {
   let PrintMethod = "printAddSubImm";

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-binop.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-binop.mir?rev=297874&r1=297873&r2=297874&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-binop.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-binop.mir Wed Mar 15 14:20:59 2017
@@ -7,6 +7,8 @@
   define void @add_s64_gpr() { ret void }
 
   define void @add_imm_s32_gpr() { ret void }
+  define void @add_imm_s64_gpr() { ret void }
+
   define void @add_imm_s32_gpr_bb() { ret void }
 
   define void @sub_s32_gpr() { ret void }
@@ -140,6 +142,33 @@ body:             |
 ...
 
 ---
+# CHECK-LABEL: name: add_imm_s64_gpr
+name:            add_imm_s64_gpr
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr64sp }
+# CHECK-NEXT:  - { id: 1, class: gpr64 }
+# CHECK-NEXT:  - { id: 2, class: gpr64sp }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %x0
+# CHECK:    %2 = ADDXri %0, 1, 0
+body:             |
+  bb.0:
+    liveins: %x0, %w1
+
+    %0(s64) = COPY %x0
+    %1(s64) = G_CONSTANT 1
+    %2(s64) = G_ADD %0, %1
+...
+
+---
 # CHECK-LABEL: name: add_imm_s32_gpr_bb
 name:            add_imm_s32_gpr_bb
 legalized:       true