[llvm] r297856 - [GlobalISel][AArch64] Split out select tests. NFC.
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 15 09:29:37 PDT 2017
Author: ab
Date: Wed Mar 15 11:29:37 2017
New Revision: 297856
URL: http://llvm.org/viewvc/llvm-project?rev=297856&view=rev
Log:
[GlobalISel][AArch64] Split out select tests. NFC.
The test has grown enough to be annoying to navigate.
While there, Remove unnecessary RUNs, and cleanup a couple comments.
Added:
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-binop.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-br.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-casts.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-property.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-store.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-xor.mir
- copied, changed from r297855, llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect-xor.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select.mir
Removed:
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect-xor.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
Removed: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect-xor.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect-xor.mir?rev=297855&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect-xor.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect-xor.mir (removed)
@@ -1,165 +0,0 @@
-# RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=IOS
-# RUN: llc -O0 -mtriple=aarch64-linux-gnu -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LINUX-DEFAULT
-# RUN: llc -O0 -mtriple=aarch64-linux-gnu -relocation-model=pic -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LINUX-PIC
-
-# Test the instruction selector.
-# As we support more instructions, we need to split this up.
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
-
- define void @xor_s32_gpr() { ret void }
- define void @xor_s64_gpr() { ret void }
- define void @xor_constant_n1_s32_gpr() { ret void }
- define void @xor_constant_n1_s64_gpr() { ret void }
- define void @xor_constant_n1_s32_gpr_2bb() { ret void }
-
-...
-
----
-# Check that we select a 32-bit GPR G_XOR into EORWrr on GPR32.
-# Also check that we constrain the register class of the COPY to GPR32.
-# CHECK-LABEL: name: xor_s32_gpr
-name: xor_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %1 = COPY %w1
-# CHECK: %2 = EORWrr %0, %1
-body: |
- bb.0:
- liveins: %w0, %w1
-
- %0(s32) = COPY %w0
- %1(s32) = COPY %w1
- %2(s32) = G_XOR %0, %1
-...
-
----
-# Same as xor_s64_gpr, for 64-bit operations.
-# CHECK-LABEL: name: xor_s64_gpr
-name: xor_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-# CHECK-NEXT: - { id: 2, class: gpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %x1
-# CHECK: %2 = EORXrr %0, %1
-body: |
- bb.0:
- liveins: %x0, %x1
-
- %0(s64) = COPY %x0
- %1(s64) = COPY %x1
- %2(s64) = G_XOR %0, %1
-...
-
----
-# Check that we select a 32-bit GPR G_XOR into EORWrr on GPR32.
-# Also check that we constrain the register class of the COPY to GPR32.
-# CHECK-LABEL: name: xor_constant_n1_s32_gpr
-name: xor_constant_n1_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %2 = ORNWrr %wzr, %0
-body: |
- bb.0:
- liveins: %w0
-
- %0(s32) = COPY %w0
- %1(s32) = G_CONSTANT i64 -1
- %2(s32) = G_XOR %0, %1
-...
-
----
-# Same as xor_constant_n1_s64_gpr, for 64-bit operations.
-# CHECK-LABEL: name: xor_constant_n1_s64_gpr
-name: xor_constant_n1_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-# CHECK-NEXT: - { id: 2, class: gpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %2 = ORNXrr %xzr, %0
-body: |
- bb.0:
- liveins: %x0
-
- %0(s64) = COPY %x0
- %1(s64) = G_CONSTANT i64 -1
- %2(s64) = G_XOR %0, %1
-...
-
----
-# Check that we can obtain constants from other basic blocks.
-# CHECK-LABEL: name: xor_constant_n1_s32_gpr_2bb
-name: xor_constant_n1_s32_gpr_2bb
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: B %bb.1
-# CHECK: %0 = COPY %w0
-# CHECK: %2 = ORNWrr %wzr, %0
-
-body: |
- bb.0:
- liveins: %w0, %w1
- successors: %bb.1
- %1(s32) = G_CONSTANT i64 -1
- G_BR %bb.1
- bb.1:
- %0(s32) = COPY %w0
- %2(s32) = G_XOR %0, %1
-...
Removed: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir?rev=297855&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (removed)
@@ -1,2660 +0,0 @@
-# RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=IOS
-# RUN: llc -O0 -mtriple=aarch64-linux-gnu -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LINUX-DEFAULT
-# RUN: llc -O0 -mtriple=aarch64-linux-gnu -relocation-model=pic -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LINUX-PIC
-
-# Test the instruction selector.
-# As we support more instructions, we need to split this up.
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
-
- define void @add_s32_gpr() { ret void }
- define void @add_s64_gpr() { ret void }
-
- define void @add_imm_s32_gpr() { ret void }
- define void @add_imm_s32_gpr_bb() { ret void }
-
- define void @sub_s32_gpr() { ret void }
- define void @sub_s64_gpr() { ret void }
-
- define void @or_s32_gpr() { ret void }
- define void @or_s64_gpr() { ret void }
- define void @or_v2s32_fpr() { ret void }
-
- define void @and_s32_gpr() { ret void }
- define void @and_s64_gpr() { ret void }
-
- define void @shl_s32_gpr() { ret void }
- define void @shl_s64_gpr() { ret void }
-
- define void @lshr_s32_gpr() { ret void }
- define void @lshr_s64_gpr() { ret void }
-
- define void @ashr_s32_gpr() { ret void }
- define void @ashr_s64_gpr() { ret void }
-
- define void @mul_s32_gpr() { ret void }
- define void @mul_s64_gpr() { ret void }
-
- define void @mulh_s64_gpr() { ret void }
-
- define void @sdiv_s32_gpr() { ret void }
- define void @sdiv_s64_gpr() { ret void }
-
- define void @udiv_s32_gpr() { ret void }
- define void @udiv_s64_gpr() { ret void }
-
- define void @fadd_s32_gpr() { ret void }
- define void @fadd_s64_gpr() { ret void }
-
- define void @fsub_s32_gpr() { ret void }
- define void @fsub_s64_gpr() { ret void }
-
- define void @fmul_s32_gpr() { ret void }
- define void @fmul_s64_gpr() { ret void }
-
- define void @fdiv_s32_gpr() { ret void }
- define void @fdiv_s64_gpr() { ret void }
-
- define void @sitofp_s32_s32_fpr() { ret void }
- define void @sitofp_s32_s64_fpr() { ret void }
- define void @sitofp_s64_s32_fpr() { ret void }
- define void @sitofp_s64_s64_fpr() { ret void }
-
- define void @uitofp_s32_s32_fpr() { ret void }
- define void @uitofp_s32_s64_fpr() { ret void }
- define void @uitofp_s64_s32_fpr() { ret void }
- define void @uitofp_s64_s64_fpr() { ret void }
-
- define void @fptosi_s32_s32_gpr() { ret void }
- define void @fptosi_s32_s64_gpr() { ret void }
- define void @fptosi_s64_s32_gpr() { ret void }
- define void @fptosi_s64_s64_gpr() { ret void }
-
- define void @fptoui_s32_s32_gpr() { ret void }
- define void @fptoui_s32_s64_gpr() { ret void }
- define void @fptoui_s64_s32_gpr() { ret void }
- define void @fptoui_s64_s64_gpr() { ret void }
-
- define void @fptrunc() { ret void }
- define void @fpext() { ret void }
-
- define void @unconditional_br() { ret void }
- define void @conditional_br() { ret void }
- define void @indirect_br() { ret void }
-
- define void @load_s64_gpr(i64* %addr) { ret void }
- define void @load_s32_gpr(i32* %addr) { ret void }
- define void @load_s16_gpr(i16* %addr) { ret void }
- define void @load_s8_gpr(i8* %addr) { ret void }
- define void @load_s64_fpr(i64* %addr) { ret void }
- define void @load_s32_fpr(i32* %addr) { ret void }
- define void @load_s16_fpr(i16* %addr) { ret void }
- define void @load_s8_fpr(i8* %addr) { ret void }
-
- define void @store_s64_gpr(i64* %addr) { ret void }
- define void @store_s32_gpr(i32* %addr) { ret void }
- define void @store_s16_gpr(i16* %addr) { ret void }
- define void @store_s8_gpr(i8* %addr) { ret void }
- define void @store_s64_fpr(i64* %addr) { ret void }
- define void @store_s32_fpr(i32* %addr) { ret void }
-
- define void @frame_index() {
- %ptr0 = alloca i64
- ret void
- }
-
- define void @selected_property() { ret void }
-
- define i32 @const_s32() { ret i32 42 }
- define i64 @const_s64() { ret i64 1234567890123 }
-
- define i32 @fconst_s32() { ret i32 42 }
- define i64 @fconst_s64() { ret i64 1234567890123 }
-
- define i8* @gep(i8* %in) { ret i8* undef }
-
- define i8* @ptr_mask(i8* %in) { ret i8* undef }
-
- @var_local = global i8 0
- define i8* @global_local() { ret i8* undef }
-
- @var_got = external global i8
- define i8* @global_got() { ret i8* undef }
-
- define void @trunc() { ret void }
-
- define void @anyext_gpr() { ret void }
- define void @zext_gpr() { ret void }
- define void @sext_gpr() { ret void }
-
- define void @casts() { ret void }
-
- define void @bitcast_s32_gpr() { ret void }
- define void @bitcast_s32_fpr() { ret void }
- define void @bitcast_s32_gpr_fpr() { ret void }
- define void @bitcast_s32_fpr_gpr() { ret void }
- define void @bitcast_s64_gpr() { ret void }
- define void @bitcast_s64_fpr() { ret void }
- define void @bitcast_s64_gpr_fpr() { ret void }
- define void @bitcast_s64_fpr_gpr() { ret void }
-
- define void @icmp() { ret void }
- define void @fcmp() { ret void }
-
- define void @phi() { ret void }
-
- define void @select() { ret void }
-...
-
----
-# Check that we select a 32-bit GPR G_ADD into ADDWrr on GPR32.
-# Also check that we constrain the register class of the COPY to GPR32.
-# CHECK-LABEL: name: add_s32_gpr
-name: add_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %1 = COPY %w1
-# CHECK: %2 = ADDWrr %0, %1
-body: |
- bb.0:
- liveins: %w0, %w1
-
- %0(s32) = COPY %w0
- %1(s32) = COPY %w1
- %2(s32) = G_ADD %0, %1
-...
-
----
-# Same as add_s32_gpr, for 64-bit operations.
-# CHECK-LABEL: name: add_s64_gpr
-name: add_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-# CHECK-NEXT: - { id: 2, class: gpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %x1
-# CHECK: %2 = ADDXrr %0, %1
-body: |
- bb.0:
- liveins: %x0, %x1
-
- %0(s64) = COPY %x0
- %1(s64) = COPY %x1
- %2(s64) = G_ADD %0, %1
-...
-
----
-# Check that we select a 32-bit GPR G_ADD into ADDWrr on GPR32.
-# Also check that we constrain the register class of the COPY to GPR32.
-# CHECK-LABEL: name: add_imm_s32_gpr
-name: add_imm_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32sp }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: gpr32sp }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %2 = ADDWri %0, 1, 0
-body: |
- bb.0:
- liveins: %w0, %w1
-
- %0(s32) = COPY %w0
- %1(s32) = G_CONSTANT 1
- %2(s32) = G_ADD %0, %1
-...
-
----
-# Check that we select a 32-bit GPR G_ADD into ADDWrr on GPR32.
-# Also check that we constrain the register class of the COPY to GPR32.
-# CHECK-LABEL: name: add_imm_s32_gpr_bb
-name: add_imm_s32_gpr_bb
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32sp }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: gpr32sp }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: bb.1:
-# CHECK: %2 = ADDWri %0, 1, 0
-body: |
- bb.0:
- liveins: %w0, %w1
- successors: %bb.1
-
- %0(s32) = COPY %w0
- %1(s32) = G_CONSTANT 1
- G_BR %bb.1
-
- bb.1:
- %2(s32) = G_ADD %0, %1
-...
-
----
-# Same as add_s32_gpr, for G_SUB operations.
-# CHECK-LABEL: name: sub_s32_gpr
-name: sub_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %1 = COPY %w1
-# CHECK: %2 = SUBSWrr %0, %1
-body: |
- bb.0:
- liveins: %w0, %w1
-
- %0(s32) = COPY %w0
- %1(s32) = COPY %w1
- %2(s32) = G_SUB %0, %1
-...
-
----
-# Same as add_s64_gpr, for G_SUB operations.
-# CHECK-LABEL: name: sub_s64_gpr
-name: sub_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-# CHECK-NEXT: - { id: 2, class: gpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %x1
-# CHECK: %2 = SUBSXrr %0, %1
-body: |
- bb.0:
- liveins: %x0, %x1
-
- %0(s64) = COPY %x0
- %1(s64) = COPY %x1
- %2(s64) = G_SUB %0, %1
-...
-
----
-# Same as add_s32_gpr, for G_OR operations.
-# CHECK-LABEL: name: or_s32_gpr
-name: or_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %1 = COPY %w1
-# CHECK: %2 = ORRWrr %0, %1
-body: |
- bb.0:
- liveins: %w0, %w1
-
- %0(s32) = COPY %w0
- %1(s32) = COPY %w1
- %2(s32) = G_OR %0, %1
-...
-
----
-# Same as add_s64_gpr, for G_OR operations.
-# CHECK-LABEL: name: or_s64_gpr
-name: or_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-# CHECK-NEXT: - { id: 2, class: gpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %x1
-# CHECK: %2 = ORRXrr %0, %1
-body: |
- bb.0:
- liveins: %x0, %x1
-
- %0(s64) = COPY %x0
- %1(s64) = COPY %x1
- %2(s64) = G_OR %0, %1
-...
-
----
-# 64-bit G_OR on vector registers.
-# CHECK-LABEL: name: or_v2s32_fpr
-name: or_v2s32_fpr
-legalized: true
-regBankSelected: true
-#
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr64 }
-# CHECK-NEXT: - { id: 1, class: fpr64 }
-# CHECK-NEXT: - { id: 2, class: fpr64 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
- - { id: 2, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %d0
-# CHECK: %1 = COPY %d1
-# The actual OR does not matter as long as it is operating
-# on 64-bit width vector.
-# CHECK: %2 = ORRv8i8 %0, %1
-body: |
- bb.0:
- liveins: %d0, %d1
-
- %0(<2 x s32>) = COPY %d0
- %1(<2 x s32>) = COPY %d1
- %2(<2 x s32>) = G_OR %0, %1
-...
-
----
-# Same as add_s32_gpr, for G_AND operations.
-# CHECK-LABEL: name: and_s32_gpr
-name: and_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %1 = COPY %w1
-# CHECK: %2 = ANDWrr %0, %1
-body: |
- bb.0:
- liveins: %w0, %w1
-
- %0(s32) = COPY %w0
- %1(s32) = COPY %w1
- %2(s32) = G_AND %0, %1
-...
-
----
-# Same as add_s64_gpr, for G_AND operations.
-# CHECK-LABEL: name: and_s64_gpr
-name: and_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-# CHECK-NEXT: - { id: 2, class: gpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %x1
-# CHECK: %2 = ANDXrr %0, %1
-body: |
- bb.0:
- liveins: %x0, %x1
-
- %0(s64) = COPY %x0
- %1(s64) = COPY %x1
- %2(s64) = G_AND %0, %1
-...
-
----
-# Same as add_s32_gpr, for G_SHL operations.
-# CHECK-LABEL: name: shl_s32_gpr
-name: shl_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %1 = COPY %w1
-# CHECK: %2 = LSLVWr %0, %1
-body: |
- bb.0:
- liveins: %w0, %w1
-
- %0(s32) = COPY %w0
- %1(s32) = COPY %w1
- %2(s32) = G_SHL %0, %1
-...
-
----
-# Same as add_s64_gpr, for G_SHL operations.
-# CHECK-LABEL: name: shl_s64_gpr
-name: shl_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-# CHECK-NEXT: - { id: 2, class: gpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %x1
-# CHECK: %2 = LSLVXr %0, %1
-body: |
- bb.0:
- liveins: %x0, %x1
-
- %0(s64) = COPY %x0
- %1(s64) = COPY %x1
- %2(s64) = G_SHL %0, %1
-...
-
----
-# Same as add_s32_gpr, for G_LSHR operations.
-# CHECK-LABEL: name: lshr_s32_gpr
-name: lshr_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %1 = COPY %w1
-# CHECK: %2 = LSRVWr %0, %1
-body: |
- bb.0:
- liveins: %w0, %w1
-
- %0(s32) = COPY %w0
- %1(s32) = COPY %w1
- %2(s32) = G_LSHR %0, %1
-...
-
----
-# Same as add_s64_gpr, for G_LSHR operations.
-# CHECK-LABEL: name: lshr_s64_gpr
-name: lshr_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-# CHECK-NEXT: - { id: 2, class: gpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %x1
-# CHECK: %2 = LSRVXr %0, %1
-body: |
- bb.0:
- liveins: %x0, %x1
-
- %0(s64) = COPY %x0
- %1(s64) = COPY %x1
- %2(s64) = G_LSHR %0, %1
-...
-
----
-# Same as add_s32_gpr, for G_ASHR operations.
-# CHECK-LABEL: name: ashr_s32_gpr
-name: ashr_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %1 = COPY %w1
-# CHECK: %2 = ASRVWr %0, %1
-body: |
- bb.0:
- liveins: %w0, %w1
-
- %0(s32) = COPY %w0
- %1(s32) = COPY %w1
- %2(s32) = G_ASHR %0, %1
-...
-
----
-# Same as add_s64_gpr, for G_ASHR operations.
-# CHECK-LABEL: name: ashr_s64_gpr
-name: ashr_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-# CHECK-NEXT: - { id: 2, class: gpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %x1
-# CHECK: %2 = ASRVXr %0, %1
-body: |
- bb.0:
- liveins: %x0, %x1
-
- %0(s64) = COPY %x0
- %1(s64) = COPY %x1
- %2(s64) = G_ASHR %0, %1
-...
-
----
-# Check that we select s32 GPR G_MUL. This is trickier than other binops because
-# there is only MADDWrrr, and we have to use the WZR physreg.
-# CHECK-LABEL: name: mul_s32_gpr
-name: mul_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %1 = COPY %w1
-# CHECK: %2 = MADDWrrr %0, %1, %wzr
-body: |
- bb.0:
- liveins: %w0, %w1
-
- %0(s32) = COPY %w0
- %1(s32) = COPY %w1
- %2(s32) = G_MUL %0, %1
-...
-
----
-# Same as mul_s32_gpr for the s64 type.
-# CHECK-LABEL: name: mul_s64_gpr
-name: mul_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-# CHECK-NEXT: - { id: 2, class: gpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %x1
-# CHECK: %2 = MADDXrrr %0, %1, %xzr
-body: |
- bb.0:
- liveins: %x0, %x1
-
- %0(s64) = COPY %x0
- %1(s64) = COPY %x1
- %2(s64) = G_MUL %0, %1
-...
-
----
-# Same as mul_s32_gpr for the s64 type.
-# CHECK-LABEL: name: mulh_s64_gpr
-name: mulh_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-# CHECK-NEXT: - { id: 2, class: gpr64 }
-# CHECK-NEXT: - { id: 3, class: gpr64 }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %x1
-# CHECK: %2 = SMULHrr %0, %1
-# CHECK: %3 = UMULHrr %0, %1
-body: |
- bb.0:
- liveins: %x0, %x1
-
- %0:gpr(s64) = COPY %x0
- %1:gpr(s64) = COPY %x1
- %2:gpr(s64) = G_SMULH %0, %1
- %3:gpr(s64) = G_UMULH %0, %1
-...
-
----
-# Same as add_s32_gpr, for G_SDIV operations.
-# CHECK-LABEL: name: sdiv_s32_gpr
-name: sdiv_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %1 = COPY %w1
-# CHECK: %2 = SDIVWr %0, %1
-body: |
- bb.0:
- liveins: %w0, %w1
-
- %0(s32) = COPY %w0
- %1(s32) = COPY %w1
- %2(s32) = G_SDIV %0, %1
-...
-
----
-# Same as add_s64_gpr, for G_SDIV operations.
-# CHECK-LABEL: name: sdiv_s64_gpr
-name: sdiv_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-# CHECK-NEXT: - { id: 2, class: gpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %x1
-# CHECK: %2 = SDIVXr %0, %1
-body: |
- bb.0:
- liveins: %x0, %x1
-
- %0(s64) = COPY %x0
- %1(s64) = COPY %x1
- %2(s64) = G_SDIV %0, %1
-...
-
----
-# Same as add_s32_gpr, for G_UDIV operations.
-# CHECK-LABEL: name: udiv_s32_gpr
-name: udiv_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %1 = COPY %w1
-# CHECK: %2 = UDIVWr %0, %1
-body: |
- bb.0:
- liveins: %w0, %w1
-
- %0(s32) = COPY %w0
- %1(s32) = COPY %w1
- %2(s32) = G_UDIV %0, %1
-...
-
----
-# Same as add_s64_gpr, for G_UDIV operations.
-# CHECK-LABEL: name: udiv_s64_gpr
-name: udiv_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-# CHECK-NEXT: - { id: 2, class: gpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %x1
-# CHECK: %2 = UDIVXr %0, %1
-body: |
- bb.0:
- liveins: %x0, %x1
-
- %0(s64) = COPY %x0
- %1(s64) = COPY %x1
- %2(s64) = G_UDIV %0, %1
-...
-
----
-# Check that we select a s32 FPR G_FADD into FADDSrr.
-# CHECK-LABEL: name: fadd_s32_gpr
-name: fadd_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr32 }
-# CHECK-NEXT: - { id: 1, class: fpr32 }
-# CHECK-NEXT: - { id: 2, class: fpr32 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
- - { id: 2, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %s0
-# CHECK: %1 = COPY %s1
-# CHECK: %2 = FADDSrr %0, %1
-body: |
- bb.0:
- liveins: %s0, %s1
-
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
- %2(s32) = G_FADD %0, %1
-...
-
----
-# CHECK-LABEL: name: fadd_s64_gpr
-name: fadd_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr64 }
-# CHECK-NEXT: - { id: 1, class: fpr64 }
-# CHECK-NEXT: - { id: 2, class: fpr64 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
- - { id: 2, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %d0
-# CHECK: %1 = COPY %d1
-# CHECK: %2 = FADDDrr %0, %1
-body: |
- bb.0:
- liveins: %d0, %d1
-
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
- %2(s64) = G_FADD %0, %1
-...
-
----
-# CHECK-LABEL: name: fsub_s32_gpr
-name: fsub_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr32 }
-# CHECK-NEXT: - { id: 1, class: fpr32 }
-# CHECK-NEXT: - { id: 2, class: fpr32 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
- - { id: 2, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %s0
-# CHECK: %1 = COPY %s1
-# CHECK: %2 = FSUBSrr %0, %1
-body: |
- bb.0:
- liveins: %s0, %s1
-
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
- %2(s32) = G_FSUB %0, %1
-...
-
----
-# CHECK-LABEL: name: fsub_s64_gpr
-name: fsub_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr64 }
-# CHECK-NEXT: - { id: 1, class: fpr64 }
-# CHECK-NEXT: - { id: 2, class: fpr64 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
- - { id: 2, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %d0
-# CHECK: %1 = COPY %d1
-# CHECK: %2 = FSUBDrr %0, %1
-body: |
- bb.0:
- liveins: %d0, %d1
-
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
- %2(s64) = G_FSUB %0, %1
-...
-
----
-# CHECK-LABEL: name: fmul_s32_gpr
-name: fmul_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr32 }
-# CHECK-NEXT: - { id: 1, class: fpr32 }
-# CHECK-NEXT: - { id: 2, class: fpr32 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
- - { id: 2, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %s0
-# CHECK: %1 = COPY %s1
-# CHECK: %2 = FMULSrr %0, %1
-body: |
- bb.0:
- liveins: %s0, %s1
-
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
- %2(s32) = G_FMUL %0, %1
-...
-
----
-# CHECK-LABEL: name: fmul_s64_gpr
-name: fmul_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr64 }
-# CHECK-NEXT: - { id: 1, class: fpr64 }
-# CHECK-NEXT: - { id: 2, class: fpr64 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
- - { id: 2, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %d0
-# CHECK: %1 = COPY %d1
-# CHECK: %2 = FMULDrr %0, %1
-body: |
- bb.0:
- liveins: %d0, %d1
-
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
- %2(s64) = G_FMUL %0, %1
-...
-
----
-# CHECK-LABEL: name: fdiv_s32_gpr
-name: fdiv_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr32 }
-# CHECK-NEXT: - { id: 1, class: fpr32 }
-# CHECK-NEXT: - { id: 2, class: fpr32 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
- - { id: 2, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %s0
-# CHECK: %1 = COPY %s1
-# CHECK: %2 = FDIVSrr %0, %1
-body: |
- bb.0:
- liveins: %s0, %s1
-
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
- %2(s32) = G_FDIV %0, %1
-...
-
----
-# CHECK-LABEL: name: fdiv_s64_gpr
-name: fdiv_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr64 }
-# CHECK-NEXT: - { id: 1, class: fpr64 }
-# CHECK-NEXT: - { id: 2, class: fpr64 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
- - { id: 2, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %d0
-# CHECK: %1 = COPY %d1
-# CHECK: %2 = FDIVDrr %0, %1
-body: |
- bb.0:
- liveins: %d0, %d1
-
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
- %2(s64) = G_FDIV %0, %1
-...
-
----
-# CHECK-LABEL: name: sitofp_s32_s32_fpr
-name: sitofp_s32_s32_fpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: fpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %1 = SCVTFUWSri %0
-body: |
- bb.0:
- liveins: %w0
-
- %0(s32) = COPY %w0
- %1(s32) = G_SITOFP %0
-...
-
----
-# CHECK-LABEL: name: sitofp_s32_s64_fpr
-name: sitofp_s32_s64_fpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64 }
-# CHECK-NEXT: - { id: 1, class: fpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = SCVTFUXSri %0
-body: |
- bb.0:
- liveins: %x0
-
- %0(s64) = COPY %x0
- %1(s32) = G_SITOFP %0
-...
-
----
-# CHECK-LABEL: name: sitofp_s64_s32_fpr
-name: sitofp_s64_s32_fpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: fpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %1 = SCVTFUWDri %0
-body: |
- bb.0:
- liveins: %w0
-
- %0(s32) = COPY %w0
- %1(s64) = G_SITOFP %0
-...
-
----
-# CHECK-LABEL: name: sitofp_s64_s64_fpr
-name: sitofp_s64_s64_fpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64 }
-# CHECK-NEXT: - { id: 1, class: fpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = SCVTFUXDri %0
-body: |
- bb.0:
- liveins: %x0
-
- %0(s64) = COPY %x0
- %1(s64) = G_SITOFP %0
-...
-
----
-# CHECK-LABEL: name: uitofp_s32_s32_fpr
-name: uitofp_s32_s32_fpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: fpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %1 = UCVTFUWSri %0
-body: |
- bb.0:
- liveins: %w0
-
- %0(s32) = COPY %w0
- %1(s32) = G_UITOFP %0
-...
-
----
-# CHECK-LABEL: name: uitofp_s32_s64_fpr
-name: uitofp_s32_s64_fpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64 }
-# CHECK-NEXT: - { id: 1, class: fpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = UCVTFUXSri %0
-body: |
- bb.0:
- liveins: %x0
-
- %0(s64) = COPY %x0
- %1(s32) = G_UITOFP %0
-...
-
----
-# CHECK-LABEL: name: uitofp_s64_s32_fpr
-name: uitofp_s64_s32_fpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: fpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %1 = UCVTFUWDri %0
-body: |
- bb.0:
- liveins: %w0
-
- %0(s32) = COPY %w0
- %1(s64) = G_UITOFP %0
-...
-
----
-# CHECK-LABEL: name: uitofp_s64_s64_fpr
-name: uitofp_s64_s64_fpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64 }
-# CHECK-NEXT: - { id: 1, class: fpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = UCVTFUXDri %0
-body: |
- bb.0:
- liveins: %x0
-
- %0(s64) = COPY %x0
- %1(s64) = G_UITOFP %0
-...
-
----
-# CHECK-LABEL: name: fptosi_s32_s32_gpr
-name: fptosi_s32_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %s0
-# CHECK: %1 = FCVTZSUWSr %0
-body: |
- bb.0:
- liveins: %s0
-
- %0(s32) = COPY %s0
- %1(s32) = G_FPTOSI %0
-...
-
----
-# CHECK-LABEL: name: fptosi_s32_s64_gpr
-name: fptosi_s32_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr64 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %d0
-# CHECK: %1 = FCVTZSUWDr %0
-body: |
- bb.0:
- liveins: %d0
-
- %0(s64) = COPY %d0
- %1(s32) = G_FPTOSI %0
-...
-
----
-# CHECK-LABEL: name: fptosi_s64_s32_gpr
-name: fptosi_s64_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %s0
-# CHECK: %1 = FCVTZSUXSr %0
-body: |
- bb.0:
- liveins: %s0
-
- %0(s32) = COPY %s0
- %1(s64) = G_FPTOSI %0
-...
-
----
-# CHECK-LABEL: name: fptosi_s64_s64_gpr
-name: fptosi_s64_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr64 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %d0
-# CHECK: %1 = FCVTZSUXDr %0
-body: |
- bb.0:
- liveins: %d0
-
- %0(s64) = COPY %d0
- %1(s64) = G_FPTOSI %0
-...
-
----
-# CHECK-LABEL: name: fptoui_s32_s32_gpr
-name: fptoui_s32_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %s0
-# CHECK: %1 = FCVTZUUWSr %0
-body: |
- bb.0:
- liveins: %s0
-
- %0(s32) = COPY %s0
- %1(s32) = G_FPTOUI %0
-...
-
----
-# CHECK-LABEL: name: fptoui_s32_s64_gpr
-name: fptoui_s32_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr64 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %d0
-# CHECK: %1 = FCVTZUUWDr %0
-body: |
- bb.0:
- liveins: %d0
-
- %0(s64) = COPY %d0
- %1(s32) = G_FPTOUI %0
-...
-
----
-# CHECK-LABEL: name: fptoui_s64_s32_gpr
-name: fptoui_s64_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %s0
-# CHECK: %1 = FCVTZUUXSr %0
-body: |
- bb.0:
- liveins: %s0
-
- %0(s32) = COPY %s0
- %1(s64) = G_FPTOUI %0
-...
-
----
-# CHECK-LABEL: name: fptoui_s64_s64_gpr
-name: fptoui_s64_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr64 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %d0
-# CHECK: %1 = FCVTZUUXDr %0
-body: |
- bb.0:
- liveins: %d0
-
- %0(s64) = COPY %d0
- %1(s64) = G_FPTOUI %0
-...
-
----
-# CHECK-LABEL: name: fptrunc
-name: fptrunc
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK: - { id: 0, class: fpr64 }
-# CHECK: - { id: 1, class: fpr32 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %d0
-# CHECK: %1 = FCVTSDr %0
-body: |
- bb.0:
- liveins: %d0
-
- %0(s64) = COPY %d0
- %1(s32) = G_FPTRUNC %0
-...
-
----
-# CHECK-LABEL: name: fpext
-name: fpext
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK: - { id: 0, class: fpr32 }
-# CHECK: - { id: 1, class: fpr64 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %s0
-# CHECK: %1 = FCVTDSr %0
-body: |
- bb.0:
- liveins: %d0
-
- %0(s32) = COPY %s0
- %1(s64) = G_FPEXT %0
-...
-
----
-# CHECK-LABEL: name: unconditional_br
-name: unconditional_br
-legalized: true
-regBankSelected: true
-
-# CHECK: body:
-# CHECK: bb.0:
-# CHECK: successors: %bb.0
-# CHECK: B %bb.0
-body: |
- bb.0:
- successors: %bb.0
-
- G_BR %bb.0
-...
-
----
-# CHECK-LABEL: name: conditional_br
-name: conditional_br
-legalized: true
-regBankSelected: true
-
-registers:
- - { id: 0, class: gpr }
-
-# CHECK: body:
-# CHECK: bb.0:
-# CHECK: TBNZW %0, 0, %bb.1
-# CHECK: B %bb.0
-body: |
- bb.0:
- successors: %bb.0, %bb.1
- %0(s1) = COPY %w0
- G_BRCOND %0(s1), %bb.1
- G_BR %bb.0
-
- bb.1:
-...
-
----
-# CHECK-LABEL: name: indirect_br
-name: indirect_br
-legalized: true
-regBankSelected: true
-
-registers:
- - { id: 0, class: gpr }
-
-# CHECK: body:
-# CHECK: bb.0:
-# CHECK: %0 = COPY %x0
-# CHECK: BR %0
-body: |
- bb.0:
- successors: %bb.0, %bb.1
- %0(p0) = COPY %x0
- G_BRINDIRECT %0(p0)
-
- bb.1:
-...
-
----
-# CHECK-LABEL: name: load_s64_gpr
-name: load_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64sp }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = LDRXui %0, 0 :: (load 8 from %ir.addr)
-body: |
- bb.0:
- liveins: %x0
-
- %0(p0) = COPY %x0
- %1(s64) = G_LOAD %0 :: (load 8 from %ir.addr)
-
-...
-
----
-# CHECK-LABEL: name: load_s32_gpr
-name: load_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64sp }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = LDRWui %0, 0 :: (load 4 from %ir.addr)
-body: |
- bb.0:
- liveins: %x0
-
- %0(p0) = COPY %x0
- %1(s32) = G_LOAD %0 :: (load 4 from %ir.addr)
-
-...
-
----
-# CHECK-LABEL: name: load_s16_gpr
-name: load_s16_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64sp }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = LDRHHui %0, 0 :: (load 2 from %ir.addr)
-body: |
- bb.0:
- liveins: %x0
-
- %0(p0) = COPY %x0
- %1(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
-
-...
-
----
-# CHECK-LABEL: name: load_s8_gpr
-name: load_s8_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64sp }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = LDRBBui %0, 0 :: (load 1 from %ir.addr)
-body: |
- bb.0:
- liveins: %x0
-
- %0(p0) = COPY %x0
- %1(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
-
-...
-
----
-# CHECK-LABEL: name: load_s64_fpr
-name: load_s64_fpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64sp }
-# CHECK-NEXT: - { id: 1, class: fpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = LDRDui %0, 0 :: (load 8 from %ir.addr)
-body: |
- bb.0:
- liveins: %x0
-
- %0(p0) = COPY %x0
- %1(s64) = G_LOAD %0 :: (load 8 from %ir.addr)
-
-...
-
----
-# CHECK-LABEL: name: load_s32_fpr
-name: load_s32_fpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64sp }
-# CHECK-NEXT: - { id: 1, class: fpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = LDRSui %0, 0 :: (load 4 from %ir.addr)
-body: |
- bb.0:
- liveins: %x0
-
- %0(p0) = COPY %x0
- %1(s32) = G_LOAD %0 :: (load 4 from %ir.addr)
-
-...
-
----
-# CHECK-LABEL: name: load_s16_fpr
-name: load_s16_fpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64sp }
-# CHECK-NEXT: - { id: 1, class: fpr16 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = LDRHui %0, 0 :: (load 2 from %ir.addr)
-body: |
- bb.0:
- liveins: %x0
-
- %0(p0) = COPY %x0
- %1(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
-
-...
-
----
-# CHECK-LABEL: name: load_s8_fpr
-name: load_s8_fpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64sp }
-# CHECK-NEXT: - { id: 1, class: fpr8 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = LDRBui %0, 0 :: (load 1 from %ir.addr)
-body: |
- bb.0:
- liveins: %x0
-
- %0(p0) = COPY %x0
- %1(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
-
-...
-
----
-# CHECK-LABEL: name: store_s64_gpr
-name: store_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64sp }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %x1
-# CHECK: STRXui %1, %0, 0 :: (store 8 into %ir.addr)
-body: |
- bb.0:
- liveins: %x0, %x1
-
- %0(p0) = COPY %x0
- %1(s64) = COPY %x1
- G_STORE %1, %0 :: (store 8 into %ir.addr)
-
-...
-
----
-# CHECK-LABEL: name: store_s32_gpr
-name: store_s32_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64sp }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %w1
-# CHECK: STRWui %1, %0, 0 :: (store 4 into %ir.addr)
-body: |
- bb.0:
- liveins: %x0, %w1
-
- %0(p0) = COPY %x0
- %1(s32) = COPY %w1
- G_STORE %1, %0 :: (store 4 into %ir.addr)
-
-...
-
----
-# CHECK-LABEL: name: store_s16_gpr
-name: store_s16_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64sp }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %w1
-# CHECK: STRHHui %1, %0, 0 :: (store 2 into %ir.addr)
-body: |
- bb.0:
- liveins: %x0, %w1
-
- %0(p0) = COPY %x0
- %1(s16) = COPY %w1
- G_STORE %1, %0 :: (store 2 into %ir.addr)
-
-...
-
----
-# CHECK-LABEL: name: store_s8_gpr
-name: store_s8_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64sp }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %w1
-# CHECK: STRBBui %1, %0, 0 :: (store 1 into %ir.addr)
-body: |
- bb.0:
- liveins: %x0, %w1
-
- %0(p0) = COPY %x0
- %1(s8) = COPY %w1
- G_STORE %1, %0 :: (store 1 into %ir.addr)
-
-...
-
----
-# CHECK-LABEL: name: store_s64_fpr
-name: store_s64_fpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64sp }
-# CHECK-NEXT: - { id: 1, class: fpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %d1
-# CHECK: STRDui %1, %0, 0 :: (store 8 into %ir.addr)
-body: |
- bb.0:
- liveins: %x0, %d1
-
- %0(p0) = COPY %x0
- %1(s64) = COPY %d1
- G_STORE %1, %0 :: (store 8 into %ir.addr)
-
-...
-
----
-# CHECK-LABEL: name: store_s32_fpr
-name: store_s32_fpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64sp }
-# CHECK-NEXT: - { id: 1, class: fpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %s1
-# CHECK: STRSui %1, %0, 0 :: (store 4 into %ir.addr)
-body: |
- bb.0:
- liveins: %x0, %s1
-
- %0(p0) = COPY %x0
- %1(s32) = COPY %s1
- G_STORE %1, %0 :: (store 4 into %ir.addr)
-
-...
-
----
-# CHECK-LABEL: name: frame_index
-name: frame_index
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64sp }
-registers:
- - { id: 0, class: gpr }
-
-stack:
- - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
-
-# CHECK: body:
-# CHECK: %0 = ADDXri %stack.0.ptr0, 0, 0
-body: |
- bb.0:
- %0(p0) = G_FRAME_INDEX %stack.0.ptr0
-...
-
----
-# Check that we set the "selected" property.
-# CHECK-LABEL: name: selected_property
-# CHECK: legalized: true
-# CHECK-NEXT: regBankSelected: true
-# CHECK-NEXT: selected: true
-name: selected_property
-legalized: true
-regBankSelected: true
-selected: false
-body: |
- bb.0:
-...
-
----
-# CHECK-LABEL: name: const_s32
-name: const_s32
-legalized: true
-regBankSelected: true
-registers:
- - { id: 0, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = MOVi32imm 42
-body: |
- bb.0:
- %0(s32) = G_CONSTANT i32 42
-...
-
----
-# CHECK-LABEL: name: const_s64
-name: const_s64
-legalized: true
-regBankSelected: true
-registers:
- - { id: 0, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = MOVi64imm 1234567890123
-body: |
- bb.0:
- %0(s64) = G_CONSTANT i64 1234567890123
-...
-
----
-# CHECK-LABEL: name: fconst_s32
-name: fconst_s32
-legalized: true
-regBankSelected: true
-registers:
- - { id: 0, class: fpr }
-
-# CHECK: body:
-# CHECK: [[TMP:%[0-9]+]] = MOVi32imm 1080033280
-# CHECK: %0 = COPY [[TMP]]
-body: |
- bb.0:
- %0(s32) = G_FCONSTANT float 3.5
-...
-
----
-# CHECK-LABEL: name: fconst_s64
-name: fconst_s64
-legalized: true
-regBankSelected: true
-registers:
- - { id: 0, class: fpr }
-
-# CHECK: body:
-# CHECK: [[TMP:%[0-9]+]] = MOVi64imm 4607182418800017408
-# CHECK: %0 = COPY [[TMP]]
-body: |
- bb.0:
- %0(s64) = G_FCONSTANT double 1.0
-...
-
----
-# CHECK-LABEL: name: gep
-name: gep
-legalized: true
-regBankSelected: true
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-
-# CHECK: body:
-# CHECK: %1 = MOVi64imm 42
-# CHECK: %2 = ADDXrr %0, %1
-body: |
- bb.0:
- liveins: %x0
- %0(p0) = COPY %x0
- %1(s64) = G_CONSTANT i64 42
- %2(p0) = G_GEP %0, %1(s64)
-...
-
----
-# CHECK-LABEL: name: ptr_mask
-name: ptr_mask
-legalized: true
-regBankSelected: true
-
-# CHECK: body:
-# CHECK: %1 = ANDXri %0, 8060
-body: |
- bb.0:
- liveins: %x0
- %0:gpr(p0) = COPY %x0
- %1:gpr(p0) = G_PTR_MASK %0, 3
-...
-
----
-# Global defined in the same linkage unit so no GOT is needed
-# CHECK-LABEL: name: global_local
-name: global_local
-legalized: true
-regBankSelected: true
-registers:
- - { id: 0, class: gpr }
-
-# CHECK: body:
-# IOS: %0 = MOVaddr target-flags(aarch64-page) @var_local, target-flags(aarch64-pageoff, aarch64-nc) @var_local
-# LINUX-DEFAULT: %0 = MOVaddr target-flags(aarch64-page) @var_local, target-flags(aarch64-pageoff, aarch64-nc) @var_local
-# LINUX-PIC: %0 = LOADgot target-flags(aarch64-got) @var_local
-body: |
- bb.0:
- %0(p0) = G_GLOBAL_VALUE @var_local
-...
-
----
-# CHECK-LABEL: name: global_got
-name: global_got
-legalized: true
-regBankSelected: true
-registers:
- - { id: 0, class: gpr }
-
-# CHECK: body:
-# IOS: %0 = LOADgot target-flags(aarch64-got) @var_got
-# LINUX-DEFAULT: %0 = MOVaddr target-flags(aarch64-page) @var_got, target-flags(aarch64-pageoff, aarch64-nc) @var_got
-# LINUX-PIC: %0 = LOADgot target-flags(aarch64-got) @var_got
-body: |
- bb.0:
- %0(p0) = G_GLOBAL_VALUE @var_got
-...
-
----
-# CHECK-LABEL: name: trunc
-name: trunc
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: gpr64 }
-# CHECK-NEXT: - { id: 3, class: gpr32 }
-# CHECK-NEXT: - { id: 4, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
- - { id: 3, class: gpr }
- - { id: 4, class: gpr }
-
-# CHECK: body:
-# CHECK: %1 = COPY %0
-# CHECK: %3 = COPY %2.sub_32
-# CHECK: %4 = COPY %2.sub_32
-body: |
- bb.0:
- liveins: %w0, %x0
-
- %0(s32) = COPY %w0
- %1(s1) = G_TRUNC %0
-
- %2(s64) = COPY %x0
- %3(s32) = G_TRUNC %2
- %4(s8) = G_TRUNC %2
-...
-
----
-# CHECK-LABEL: name: anyext_gpr
-name: anyext_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32all }
-# CHECK-NEXT: - { id: 1, class: gpr64all }
-# CHECK-NEXT: - { id: 2, class: gpr32all }
-# CHECK-NEXT: - { id: 3, class: gpr32all }
-# CHECK-NEXT: - { id: 4, class: gpr64all }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
- - { id: 3, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %4 = SUBREG_TO_REG 0, %0, 15
-# CHECK: %1 = COPY %4
-# CHECK: %2 = COPY %w0
-# CHECK: %3 = COPY %2
-body: |
- bb.0:
- liveins: %w0
-
- %0(s32) = COPY %w0
- %1(s64) = G_ANYEXT %0
- %2(s8) = COPY %w0
- %3(s32) = G_ANYEXT %2
-...
-
----
-# CHECK-LABEL: name: zext_gpr
-name: zext_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-# CHECK-NEXT: - { id: 2, class: gpr32 }
-# CHECK-NEXT: - { id: 3, class: gpr32 }
-# CHECK-NEXT: - { id: 4, class: gpr32 }
-# CHECK-NEXT: - { id: 5, class: gpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
- - { id: 3, class: gpr }
- - { id: 4, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %5 = SUBREG_TO_REG 0, %0, 15
-# CHECK: %1 = UBFMXri %5, 0, 31
-# CHECK: %2 = COPY %w0
-# CHECK: %3 = UBFMWri %2, 0, 7
-# CHECK: %4 = UBFMWri %2, 0, 7
-body: |
- bb.0:
- liveins: %w0
-
- %0(s32) = COPY %w0
- %1(s64) = G_ZEXT %0
- %2(s8) = COPY %w0
- %3(s32) = G_ZEXT %2
- %4(s16)= G_ZEXT %2
-...
-
----
-# CHECK-LABEL: name: sext_gpr
-name: sext_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr64 }
-# CHECK-NEXT: - { id: 2, class: gpr32 }
-# CHECK-NEXT: - { id: 3, class: gpr32 }
-# CHECK-NEXT: - { id: 4, class: gpr32 }
-# CHECK-NEXT: - { id: 5, class: gpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
- - { id: 3, class: gpr }
- - { id: 4, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %5 = SUBREG_TO_REG 0, %0, 15
-# CHECK: %1 = SBFMXri %5, 0, 31
-# CHECK: %2 = COPY %w0
-# CHECK: %3 = SBFMWri %2, 0, 7
-# CHECK: %4 = SBFMWri %2, 0, 7
-body: |
- bb.0:
- liveins: %w0
-
- %0(s32) = COPY %w0
- %1(s64) = G_SEXT %0
- %2(s8) = COPY %w0
- %3(s32) = G_SEXT %2
- %4(s16) = G_SEXT %2
-...
-
----
-# CHECK-LABEL: name: casts
-name: casts
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64all }
-# CHECK-NEXT: - { id: 1, class: fpr64 }
-# CHECK-NEXT: - { id: 2, class: gpr64 }
-# CHECK-NEXT: - { id: 3, class: gpr64 }
-# CHECK-NEXT: - { id: 4, class: gpr32 }
-# CHECK-NEXT: - { id: 5, class: gpr32 }
-# CHECK-NEXT: - { id: 6, class: gpr32 }
-# CHECK-NEXT: - { id: 7, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: fpr }
- - { id: 2, class: gpr }
- - { id: 3, class: gpr }
- - { id: 4, class: gpr }
- - { id: 5, class: gpr }
- - { id: 6, class: gpr }
- - { id: 7, class: gpr }
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %0
-# CHECK: %2 = COPY %0
-# CHECK: %3 = COPY %2
-# CHECK: %4 = COPY %2.sub_32
-# CHECK: %5 = COPY %2.sub_32
-# CHECK: %6 = COPY %2.sub_32
-# CHECK: %7 = COPY %2.sub_32
-body: |
- bb.0:
- liveins: %x0
- %0(s64) = COPY %x0
- %1(<8 x s8>) = G_BITCAST %0(s64)
- %2(p0) = G_INTTOPTR %0
-
- %3(s64) = G_PTRTOINT %2
- %4(s32) = G_PTRTOINT %2
- %5(s16) = G_PTRTOINT %2
- %6(s8) = G_PTRTOINT %2
- %7(s1) = G_PTRTOINT %2
-...
-
----
-# CHECK-LABEL: name: bitcast_s32_gpr
-name: bitcast_s32_gpr
-legalized: true
-regBankSelected: true
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32all }
-# CHECK-NEXT: - { id: 1, class: gpr32all }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %1 = COPY %0
-body: |
- bb.0:
- liveins: %w0
-
- %0(s32) = COPY %w0
- %1(s32) = G_BITCAST %0
-...
-
----
-# CHECK-LABEL: name: bitcast_s32_fpr
-name: bitcast_s32_fpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr32 }
-# CHECK-NEXT: - { id: 1, class: fpr32 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %s0
-# CHECK: %1 = COPY %0
-body: |
- bb.0:
- liveins: %s0
-
- %0(s32) = COPY %s0
- %1(s32) = G_BITCAST %0
-...
-
----
-# CHECK-LABEL: name: bitcast_s32_gpr_fpr
-name: bitcast_s32_gpr_fpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32all }
-# CHECK-NEXT: - { id: 1, class: fpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %1 = COPY %0
-body: |
- bb.0:
- liveins: %w0
-
- %0(s32) = COPY %w0
- %1(s32) = G_BITCAST %0
-...
-
----
-# CHECK-LABEL: name: bitcast_s32_fpr_gpr
-name: bitcast_s32_fpr_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32all }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %s0
-# CHECK: %1 = COPY %0
-body: |
- bb.0:
- liveins: %s0
-
- %0(s32) = COPY %s0
- %1(s32) = G_BITCAST %0
-...
-
----
-# CHECK-LABEL: name: bitcast_s64_gpr
-name: bitcast_s64_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64all }
-# CHECK-NEXT: - { id: 1, class: gpr64all }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %0
-body: |
- bb.0:
- liveins: %x0
-
- %0(s64) = COPY %x0
- %1(s64) = G_BITCAST %0
-...
-
----
-# CHECK-LABEL: name: bitcast_s64_fpr
-name: bitcast_s64_fpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr64 }
-# CHECK-NEXT: - { id: 1, class: fpr64 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: fpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %d0
-# CHECK: %1 = COPY %0
-body: |
- bb.0:
- liveins: %d0
-
- %0(s64) = COPY %d0
- %1(s64) = G_BITCAST %0
-...
-
----
-# CHECK-LABEL: name: bitcast_s64_gpr_fpr
-name: bitcast_s64_gpr_fpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr64all }
-# CHECK-NEXT: - { id: 1, class: fpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: fpr }
-# CHECK: body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %0
-body: |
- bb.0:
- liveins: %x0
-
- %0(s64) = COPY %x0
- %1(s64) = G_BITCAST %0
-...
-
----
-# CHECK-LABEL: name: bitcast_s64_fpr_gpr
-name: bitcast_s64_fpr_gpr
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr64 }
-# CHECK-NEXT: - { id: 1, class: gpr64all }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: gpr }
-
-# CHECK: body:
-# CHECK: %0 = COPY %d0
-# CHECK: %1 = COPY %0
-body: |
- bb.0:
- liveins: %d0
-
- %0(s64) = COPY %d0
- %1(s64) = G_BITCAST %0
-...
-
----
-# CHECK-LABEL: name: icmp
-name: icmp
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: gpr64 }
-# CHECK-NEXT: - { id: 3, class: gpr32 }
-# CHECK-NEXT: - { id: 4, class: gpr64 }
-# CHECK-NEXT: - { id: 5, class: gpr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
- - { id: 3, class: gpr }
- - { id: 4, class: gpr }
- - { id: 5, class: gpr }
-
-# CHECK: body:
-# CHECK: %wzr = SUBSWrr %0, %0, implicit-def %nzcv
-# CHECK: %1 = CSINCWr %wzr, %wzr, 1, implicit %nzcv
-
-# CHECK: %xzr = SUBSXrr %2, %2, implicit-def %nzcv
-# CHECK: %3 = CSINCWr %wzr, %wzr, 3, implicit %nzcv
-
-# CHECK: %xzr = SUBSXrr %4, %4, implicit-def %nzcv
-# CHECK: %5 = CSINCWr %wzr, %wzr, 0, implicit %nzcv
-
-body: |
- bb.0:
- liveins: %w0, %x0
-
- %0(s32) = COPY %w0
- %1(s1) = G_ICMP intpred(eq), %0, %0
-
- %2(s64) = COPY %x0
- %3(s1) = G_ICMP intpred(uge), %2, %2
-
- %4(p0) = COPY %x0
- %5(s1) = G_ICMP intpred(ne), %4, %4
-...
-
----
-# CHECK-LABEL: name: fcmp
-name: fcmp
-legalized: true
-regBankSelected: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: fpr64 }
-# CHECK-NEXT: - { id: 3, class: gpr32 }
-# CHECK-NEXT: - { id: 4, class: gpr32 }
-# CHECK-NEXT: - { id: 5, class: gpr32 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: gpr }
- - { id: 2, class: fpr }
- - { id: 3, class: gpr }
-
-# CHECK: body:
-# CHECK: FCMPSrr %0, %0, implicit-def %nzcv
-# CHECK: [[TST_MI:%[0-9]+]] = CSINCWr %wzr, %wzr, 5, implicit %nzcv
-# CHECK: [[TST_GT:%[0-9]+]] = CSINCWr %wzr, %wzr, 13, implicit %nzcv
-# CHECK: %1 = ORRWrr [[TST_MI]], [[TST_GT]]
-
-# CHECK: FCMPDrr %2, %2, implicit-def %nzcv
-# CHECK: %3 = CSINCWr %wzr, %wzr, 4, implicit %nzcv
-
-body: |
- bb.0:
- liveins: %w0, %x0
-
- %0(s32) = COPY %s0
- %1(s1) = G_FCMP floatpred(one), %0, %0
-
- %2(s64) = COPY %d0
- %3(s1) = G_FCMP floatpred(uge), %2, %2
-
-...
-
----
-# CHECK-LABEL: name: phi
-name: phi
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: fpr32 }
-registers:
- - { id: 0, class: fpr }
- - { id: 1, class: gpr }
- - { id: 2, class: fpr }
-
-# CHECK: body:
-# CHECK: bb.1:
-# CHECK: %2 = PHI %0, %bb.0, %2, %bb.1
-
-body: |
- bb.0:
- liveins: %s0, %w0
- successors: %bb.1
- %0(s32) = COPY %s0
- %1(s1) = COPY %w0
-
- bb.1:
- successors: %bb.1, %bb.2
- %2(s32) = PHI %0, %bb.0, %2, %bb.1
- G_BRCOND %1, %bb.1
-
- bb.2:
- %s0 = COPY %2
- RET_ReallyLR implicit %s0
-...
-
----
-# CHECK-LABEL: name: select
-name: select
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr32 }
-# CHECK-NEXT: - { id: 1, class: gpr32 }
-# CHECK-NEXT: - { id: 2, class: gpr32 }
-# CHECK-NEXT: - { id: 3, class: gpr32 }
-# CHECK-NEXT: - { id: 4, class: gpr64 }
-# CHECK-NEXT: - { id: 5, class: gpr64 }
-# CHECK-NEXT: - { id: 6, class: gpr64 }
-# CHECK-NEXT: - { id: 7, class: gpr64 }
-# CHECK-NEXT: - { id: 8, class: gpr64 }
-# CHECK-NEXT: - { id: 9, class: gpr64 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
- - { id: 3, class: gpr }
- - { id: 4, class: gpr }
- - { id: 5, class: gpr }
- - { id: 6, class: gpr }
- - { id: 7, class: gpr }
- - { id: 8, class: gpr }
- - { id: 9, class: gpr }
-
-# CHECK: body:
-# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv
-# CHECK: %3 = CSELWr %1, %2, 1, implicit %nzcv
-# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv
-# CHECK: %6 = CSELXr %4, %5, 1, implicit %nzcv
-# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv
-# CHECK: %9 = CSELXr %7, %8, 1, implicit %nzcv
-body: |
- bb.0:
- liveins: %w0, %w1, %w2
- %0(s1) = COPY %w0
-
- %1(s32) = COPY %w1
- %2(s32) = COPY %w2
- %3(s32) = G_SELECT %0, %1, %2
-
- %4(s64) = COPY %x0
- %5(s64) = COPY %x1
- %6(s64) = G_SELECT %0, %4, %5
-
- %7(p0) = COPY %x0
- %8(p0) = COPY %x1
- %9(p0) = G_SELECT %0, %7, %8
-...
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-binop.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-binop.mir?rev=297856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-binop.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-binop.mir Wed Mar 15 11:29:37 2017
@@ -0,0 +1,979 @@
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+ define void @add_s32_gpr() { ret void }
+ define void @add_s64_gpr() { ret void }
+
+ define void @add_imm_s32_gpr() { ret void }
+ define void @add_imm_s32_gpr_bb() { ret void }
+
+ define void @sub_s32_gpr() { ret void }
+ define void @sub_s64_gpr() { ret void }
+
+ define void @or_s32_gpr() { ret void }
+ define void @or_s64_gpr() { ret void }
+ define void @or_v2s32_fpr() { ret void }
+
+ define void @and_s32_gpr() { ret void }
+ define void @and_s64_gpr() { ret void }
+
+ define void @shl_s32_gpr() { ret void }
+ define void @shl_s64_gpr() { ret void }
+
+ define void @lshr_s32_gpr() { ret void }
+ define void @lshr_s64_gpr() { ret void }
+
+ define void @ashr_s32_gpr() { ret void }
+ define void @ashr_s64_gpr() { ret void }
+
+ define void @mul_s32_gpr() { ret void }
+ define void @mul_s64_gpr() { ret void }
+
+ define void @mulh_s64_gpr() { ret void }
+
+ define void @sdiv_s32_gpr() { ret void }
+ define void @sdiv_s64_gpr() { ret void }
+
+ define void @udiv_s32_gpr() { ret void }
+ define void @udiv_s64_gpr() { ret void }
+
+ define void @fadd_s32_gpr() { ret void }
+ define void @fadd_s64_gpr() { ret void }
+
+ define void @fsub_s32_gpr() { ret void }
+ define void @fsub_s64_gpr() { ret void }
+
+ define void @fmul_s32_gpr() { ret void }
+ define void @fmul_s64_gpr() { ret void }
+
+ define void @fdiv_s32_gpr() { ret void }
+ define void @fdiv_s64_gpr() { ret void }
+
+...
+
+---
+# Check that we select a 32-bit GPR G_ADD into ADDWrr on GPR32.
+# Also check that we constrain the register class of the COPY to GPR32.
+# CHECK-LABEL: name: add_s32_gpr
+name: add_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = COPY %w1
+# CHECK: %2 = ADDWrr %0, %1
+body: |
+ bb.0:
+ liveins: %w0, %w1
+
+ %0(s32) = COPY %w0
+ %1(s32) = COPY %w1
+ %2(s32) = G_ADD %0, %1
+...
+
+---
+# Same as add_s32_gpr, for 64-bit operations.
+# CHECK-LABEL: name: add_s64_gpr
+name: add_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+# CHECK-NEXT: - { id: 2, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %x1
+# CHECK: %2 = ADDXrr %0, %1
+body: |
+ bb.0:
+ liveins: %x0, %x1
+
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x1
+ %2(s64) = G_ADD %0, %1
+...
+
+---
+# CHECK-LABEL: name: add_imm_s32_gpr
+name: add_imm_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32sp }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr32sp }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %2 = ADDWri %0, 1, 0
+body: |
+ bb.0:
+ liveins: %w0, %w1
+
+ %0(s32) = COPY %w0
+ %1(s32) = G_CONSTANT 1
+ %2(s32) = G_ADD %0, %1
+...
+
+---
+# CHECK-LABEL: name: add_imm_s32_gpr_bb
+name: add_imm_s32_gpr_bb
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32sp }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr32sp }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: bb.1:
+# CHECK: %2 = ADDWri %0, 1, 0
+body: |
+ bb.0:
+ liveins: %w0, %w1
+ successors: %bb.1
+
+ %0(s32) = COPY %w0
+ %1(s32) = G_CONSTANT 1
+ G_BR %bb.1
+
+ bb.1:
+ %2(s32) = G_ADD %0, %1
+...
+
+---
+# Same as add_s32_gpr, for G_SUB operations.
+# CHECK-LABEL: name: sub_s32_gpr
+name: sub_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = COPY %w1
+# CHECK: %2 = SUBSWrr %0, %1
+body: |
+ bb.0:
+ liveins: %w0, %w1
+
+ %0(s32) = COPY %w0
+ %1(s32) = COPY %w1
+ %2(s32) = G_SUB %0, %1
+...
+
+---
+# Same as add_s64_gpr, for G_SUB operations.
+# CHECK-LABEL: name: sub_s64_gpr
+name: sub_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+# CHECK-NEXT: - { id: 2, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %x1
+# CHECK: %2 = SUBSXrr %0, %1
+body: |
+ bb.0:
+ liveins: %x0, %x1
+
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x1
+ %2(s64) = G_SUB %0, %1
+...
+
+---
+# Same as add_s32_gpr, for G_OR operations.
+# CHECK-LABEL: name: or_s32_gpr
+name: or_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = COPY %w1
+# CHECK: %2 = ORRWrr %0, %1
+body: |
+ bb.0:
+ liveins: %w0, %w1
+
+ %0(s32) = COPY %w0
+ %1(s32) = COPY %w1
+ %2(s32) = G_OR %0, %1
+...
+
+---
+# Same as add_s64_gpr, for G_OR operations.
+# CHECK-LABEL: name: or_s64_gpr
+name: or_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+# CHECK-NEXT: - { id: 2, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %x1
+# CHECK: %2 = ORRXrr %0, %1
+body: |
+ bb.0:
+ liveins: %x0, %x1
+
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x1
+ %2(s64) = G_OR %0, %1
+...
+
+---
+# 64-bit G_OR on vector registers.
+# CHECK-LABEL: name: or_v2s32_fpr
+name: or_v2s32_fpr
+legalized: true
+regBankSelected: true
+#
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr64 }
+# CHECK-NEXT: - { id: 1, class: fpr64 }
+# CHECK-NEXT: - { id: 2, class: fpr64 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+ - { id: 2, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %d0
+# CHECK: %1 = COPY %d1
+# The actual OR does not matter as long as it is operating
+# on 64-bit width vector.
+# CHECK: %2 = ORRv8i8 %0, %1
+body: |
+ bb.0:
+ liveins: %d0, %d1
+
+ %0(<2 x s32>) = COPY %d0
+ %1(<2 x s32>) = COPY %d1
+ %2(<2 x s32>) = G_OR %0, %1
+...
+
+---
+# Same as add_s32_gpr, for G_AND operations.
+# CHECK-LABEL: name: and_s32_gpr
+name: and_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = COPY %w1
+# CHECK: %2 = ANDWrr %0, %1
+body: |
+ bb.0:
+ liveins: %w0, %w1
+
+ %0(s32) = COPY %w0
+ %1(s32) = COPY %w1
+ %2(s32) = G_AND %0, %1
+...
+
+---
+# Same as add_s64_gpr, for G_AND operations.
+# CHECK-LABEL: name: and_s64_gpr
+name: and_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+# CHECK-NEXT: - { id: 2, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %x1
+# CHECK: %2 = ANDXrr %0, %1
+body: |
+ bb.0:
+ liveins: %x0, %x1
+
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x1
+ %2(s64) = G_AND %0, %1
+...
+
+---
+# Same as add_s32_gpr, for G_SHL operations.
+# CHECK-LABEL: name: shl_s32_gpr
+name: shl_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = COPY %w1
+# CHECK: %2 = LSLVWr %0, %1
+body: |
+ bb.0:
+ liveins: %w0, %w1
+
+ %0(s32) = COPY %w0
+ %1(s32) = COPY %w1
+ %2(s32) = G_SHL %0, %1
+...
+
+---
+# Same as add_s64_gpr, for G_SHL operations.
+# CHECK-LABEL: name: shl_s64_gpr
+name: shl_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+# CHECK-NEXT: - { id: 2, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %x1
+# CHECK: %2 = LSLVXr %0, %1
+body: |
+ bb.0:
+ liveins: %x0, %x1
+
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x1
+ %2(s64) = G_SHL %0, %1
+...
+
+---
+# Same as add_s32_gpr, for G_LSHR operations.
+# CHECK-LABEL: name: lshr_s32_gpr
+name: lshr_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = COPY %w1
+# CHECK: %2 = LSRVWr %0, %1
+body: |
+ bb.0:
+ liveins: %w0, %w1
+
+ %0(s32) = COPY %w0
+ %1(s32) = COPY %w1
+ %2(s32) = G_LSHR %0, %1
+...
+
+---
+# Same as add_s64_gpr, for G_LSHR operations.
+# CHECK-LABEL: name: lshr_s64_gpr
+name: lshr_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+# CHECK-NEXT: - { id: 2, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %x1
+# CHECK: %2 = LSRVXr %0, %1
+body: |
+ bb.0:
+ liveins: %x0, %x1
+
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x1
+ %2(s64) = G_LSHR %0, %1
+...
+
+---
+# Same as add_s32_gpr, for G_ASHR operations.
+# CHECK-LABEL: name: ashr_s32_gpr
+name: ashr_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = COPY %w1
+# CHECK: %2 = ASRVWr %0, %1
+body: |
+ bb.0:
+ liveins: %w0, %w1
+
+ %0(s32) = COPY %w0
+ %1(s32) = COPY %w1
+ %2(s32) = G_ASHR %0, %1
+...
+
+---
+# Same as add_s64_gpr, for G_ASHR operations.
+# CHECK-LABEL: name: ashr_s64_gpr
+name: ashr_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+# CHECK-NEXT: - { id: 2, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %x1
+# CHECK: %2 = ASRVXr %0, %1
+body: |
+ bb.0:
+ liveins: %x0, %x1
+
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x1
+ %2(s64) = G_ASHR %0, %1
+...
+
+---
+# Check that we select s32 GPR G_MUL. This is trickier than other binops because
+# there is only MADDWrrr, and we have to use the WZR physreg.
+# CHECK-LABEL: name: mul_s32_gpr
+name: mul_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = COPY %w1
+# CHECK: %2 = MADDWrrr %0, %1, %wzr
+body: |
+ bb.0:
+ liveins: %w0, %w1
+
+ %0(s32) = COPY %w0
+ %1(s32) = COPY %w1
+ %2(s32) = G_MUL %0, %1
+...
+
+---
+# Same as mul_s32_gpr for the s64 type.
+# CHECK-LABEL: name: mul_s64_gpr
+name: mul_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+# CHECK-NEXT: - { id: 2, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %x1
+# CHECK: %2 = MADDXrrr %0, %1, %xzr
+body: |
+ bb.0:
+ liveins: %x0, %x1
+
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x1
+ %2(s64) = G_MUL %0, %1
+...
+
+---
+# Same as mul_s32_gpr for the s64 type.
+# CHECK-LABEL: name: mulh_s64_gpr
+name: mulh_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+# CHECK-NEXT: - { id: 2, class: gpr64 }
+# CHECK-NEXT: - { id: 3, class: gpr64 }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %x1
+# CHECK: %2 = SMULHrr %0, %1
+# CHECK: %3 = UMULHrr %0, %1
+body: |
+ bb.0:
+ liveins: %x0, %x1
+
+ %0:gpr(s64) = COPY %x0
+ %1:gpr(s64) = COPY %x1
+ %2:gpr(s64) = G_SMULH %0, %1
+ %3:gpr(s64) = G_UMULH %0, %1
+...
+
+---
+# Same as add_s32_gpr, for G_SDIV operations.
+# CHECK-LABEL: name: sdiv_s32_gpr
+name: sdiv_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = COPY %w1
+# CHECK: %2 = SDIVWr %0, %1
+body: |
+ bb.0:
+ liveins: %w0, %w1
+
+ %0(s32) = COPY %w0
+ %1(s32) = COPY %w1
+ %2(s32) = G_SDIV %0, %1
+...
+
+---
+# Same as add_s64_gpr, for G_SDIV operations.
+# CHECK-LABEL: name: sdiv_s64_gpr
+name: sdiv_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+# CHECK-NEXT: - { id: 2, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %x1
+# CHECK: %2 = SDIVXr %0, %1
+body: |
+ bb.0:
+ liveins: %x0, %x1
+
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x1
+ %2(s64) = G_SDIV %0, %1
+...
+
+---
+# Same as add_s32_gpr, for G_UDIV operations.
+# CHECK-LABEL: name: udiv_s32_gpr
+name: udiv_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = COPY %w1
+# CHECK: %2 = UDIVWr %0, %1
+body: |
+ bb.0:
+ liveins: %w0, %w1
+
+ %0(s32) = COPY %w0
+ %1(s32) = COPY %w1
+ %2(s32) = G_UDIV %0, %1
+...
+
+---
+# Same as add_s64_gpr, for G_UDIV operations.
+# CHECK-LABEL: name: udiv_s64_gpr
+name: udiv_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+# CHECK-NEXT: - { id: 2, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %x1
+# CHECK: %2 = UDIVXr %0, %1
+body: |
+ bb.0:
+ liveins: %x0, %x1
+
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x1
+ %2(s64) = G_UDIV %0, %1
+...
+
+---
+# Check that we select a s32 FPR G_FADD into FADDSrr.
+# CHECK-LABEL: name: fadd_s32_gpr
+name: fadd_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr32 }
+# CHECK-NEXT: - { id: 1, class: fpr32 }
+# CHECK-NEXT: - { id: 2, class: fpr32 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+ - { id: 2, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %s0
+# CHECK: %1 = COPY %s1
+# CHECK: %2 = FADDSrr %0, %1
+body: |
+ bb.0:
+ liveins: %s0, %s1
+
+ %0(s32) = COPY %s0
+ %1(s32) = COPY %s1
+ %2(s32) = G_FADD %0, %1
+...
+
+---
+# CHECK-LABEL: name: fadd_s64_gpr
+name: fadd_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr64 }
+# CHECK-NEXT: - { id: 1, class: fpr64 }
+# CHECK-NEXT: - { id: 2, class: fpr64 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+ - { id: 2, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %d0
+# CHECK: %1 = COPY %d1
+# CHECK: %2 = FADDDrr %0, %1
+body: |
+ bb.0:
+ liveins: %d0, %d1
+
+ %0(s64) = COPY %d0
+ %1(s64) = COPY %d1
+ %2(s64) = G_FADD %0, %1
+...
+
+---
+# CHECK-LABEL: name: fsub_s32_gpr
+name: fsub_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr32 }
+# CHECK-NEXT: - { id: 1, class: fpr32 }
+# CHECK-NEXT: - { id: 2, class: fpr32 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+ - { id: 2, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %s0
+# CHECK: %1 = COPY %s1
+# CHECK: %2 = FSUBSrr %0, %1
+body: |
+ bb.0:
+ liveins: %s0, %s1
+
+ %0(s32) = COPY %s0
+ %1(s32) = COPY %s1
+ %2(s32) = G_FSUB %0, %1
+...
+
+---
+# CHECK-LABEL: name: fsub_s64_gpr
+name: fsub_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr64 }
+# CHECK-NEXT: - { id: 1, class: fpr64 }
+# CHECK-NEXT: - { id: 2, class: fpr64 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+ - { id: 2, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %d0
+# CHECK: %1 = COPY %d1
+# CHECK: %2 = FSUBDrr %0, %1
+body: |
+ bb.0:
+ liveins: %d0, %d1
+
+ %0(s64) = COPY %d0
+ %1(s64) = COPY %d1
+ %2(s64) = G_FSUB %0, %1
+...
+
+---
+# CHECK-LABEL: name: fmul_s32_gpr
+name: fmul_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr32 }
+# CHECK-NEXT: - { id: 1, class: fpr32 }
+# CHECK-NEXT: - { id: 2, class: fpr32 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+ - { id: 2, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %s0
+# CHECK: %1 = COPY %s1
+# CHECK: %2 = FMULSrr %0, %1
+body: |
+ bb.0:
+ liveins: %s0, %s1
+
+ %0(s32) = COPY %s0
+ %1(s32) = COPY %s1
+ %2(s32) = G_FMUL %0, %1
+...
+
+---
+# CHECK-LABEL: name: fmul_s64_gpr
+name: fmul_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr64 }
+# CHECK-NEXT: - { id: 1, class: fpr64 }
+# CHECK-NEXT: - { id: 2, class: fpr64 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+ - { id: 2, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %d0
+# CHECK: %1 = COPY %d1
+# CHECK: %2 = FMULDrr %0, %1
+body: |
+ bb.0:
+ liveins: %d0, %d1
+
+ %0(s64) = COPY %d0
+ %1(s64) = COPY %d1
+ %2(s64) = G_FMUL %0, %1
+...
+
+---
+# CHECK-LABEL: name: fdiv_s32_gpr
+name: fdiv_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr32 }
+# CHECK-NEXT: - { id: 1, class: fpr32 }
+# CHECK-NEXT: - { id: 2, class: fpr32 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+ - { id: 2, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %s0
+# CHECK: %1 = COPY %s1
+# CHECK: %2 = FDIVSrr %0, %1
+body: |
+ bb.0:
+ liveins: %s0, %s1
+
+ %0(s32) = COPY %s0
+ %1(s32) = COPY %s1
+ %2(s32) = G_FDIV %0, %1
+...
+
+---
+# CHECK-LABEL: name: fdiv_s64_gpr
+name: fdiv_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr64 }
+# CHECK-NEXT: - { id: 1, class: fpr64 }
+# CHECK-NEXT: - { id: 2, class: fpr64 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+ - { id: 2, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %d0
+# CHECK: %1 = COPY %d1
+# CHECK: %2 = FDIVDrr %0, %1
+body: |
+ bb.0:
+ liveins: %d0, %d1
+
+ %0(s64) = COPY %d0
+ %1(s64) = COPY %d1
+ %2(s64) = G_FDIV %0, %1
+...
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir?rev=297856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir Wed Mar 15 11:29:37 2017
@@ -0,0 +1,404 @@
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+ define void @trunc() { ret void }
+
+ define void @anyext_gpr() { ret void }
+ define void @zext_gpr() { ret void }
+ define void @sext_gpr() { ret void }
+
+ define void @other_casts() { ret void }
+
+ define void @bitcast_s32_gpr() { ret void }
+ define void @bitcast_s32_fpr() { ret void }
+ define void @bitcast_s32_gpr_fpr() { ret void }
+ define void @bitcast_s32_fpr_gpr() { ret void }
+ define void @bitcast_s64_gpr() { ret void }
+ define void @bitcast_s64_fpr() { ret void }
+ define void @bitcast_s64_gpr_fpr() { ret void }
+ define void @bitcast_s64_fpr_gpr() { ret void }
+...
+
+---
+# CHECK-LABEL: name: trunc
+name: trunc
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr64 }
+# CHECK-NEXT: - { id: 3, class: gpr32 }
+# CHECK-NEXT: - { id: 4, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+ - { id: 3, class: gpr }
+ - { id: 4, class: gpr }
+
+# CHECK: body:
+# CHECK: %1 = COPY %0
+# CHECK: %3 = COPY %2.sub_32
+# CHECK: %4 = COPY %2.sub_32
+body: |
+ bb.0:
+ liveins: %w0, %x0
+
+ %0(s32) = COPY %w0
+ %1(s1) = G_TRUNC %0
+
+ %2(s64) = COPY %x0
+ %3(s32) = G_TRUNC %2
+ %4(s8) = G_TRUNC %2
+...
+
+---
+# CHECK-LABEL: name: anyext_gpr
+name: anyext_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32all }
+# CHECK-NEXT: - { id: 1, class: gpr64all }
+# CHECK-NEXT: - { id: 2, class: gpr32all }
+# CHECK-NEXT: - { id: 3, class: gpr32all }
+# CHECK-NEXT: - { id: 4, class: gpr64all }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+ - { id: 3, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %4 = SUBREG_TO_REG 0, %0, 15
+# CHECK: %1 = COPY %4
+# CHECK: %2 = COPY %w0
+# CHECK: %3 = COPY %2
+body: |
+ bb.0:
+ liveins: %w0
+
+ %0(s32) = COPY %w0
+ %1(s64) = G_ANYEXT %0
+ %2(s8) = COPY %w0
+ %3(s32) = G_ANYEXT %2
+...
+
+---
+# CHECK-LABEL: name: zext_gpr
+name: zext_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+# CHECK-NEXT: - { id: 2, class: gpr32 }
+# CHECK-NEXT: - { id: 3, class: gpr32 }
+# CHECK-NEXT: - { id: 4, class: gpr32 }
+# CHECK-NEXT: - { id: 5, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+ - { id: 3, class: gpr }
+ - { id: 4, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %5 = SUBREG_TO_REG 0, %0, 15
+# CHECK: %1 = UBFMXri %5, 0, 31
+# CHECK: %2 = COPY %w0
+# CHECK: %3 = UBFMWri %2, 0, 7
+# CHECK: %4 = UBFMWri %2, 0, 7
+body: |
+ bb.0:
+ liveins: %w0
+
+ %0(s32) = COPY %w0
+ %1(s64) = G_ZEXT %0
+ %2(s8) = COPY %w0
+ %3(s32) = G_ZEXT %2
+ %4(s16)= G_ZEXT %2
+...
+
+---
+# CHECK-LABEL: name: sext_gpr
+name: sext_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+# CHECK-NEXT: - { id: 2, class: gpr32 }
+# CHECK-NEXT: - { id: 3, class: gpr32 }
+# CHECK-NEXT: - { id: 4, class: gpr32 }
+# CHECK-NEXT: - { id: 5, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+ - { id: 3, class: gpr }
+ - { id: 4, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %5 = SUBREG_TO_REG 0, %0, 15
+# CHECK: %1 = SBFMXri %5, 0, 31
+# CHECK: %2 = COPY %w0
+# CHECK: %3 = SBFMWri %2, 0, 7
+# CHECK: %4 = SBFMWri %2, 0, 7
+body: |
+ bb.0:
+ liveins: %w0
+
+ %0(s32) = COPY %w0
+ %1(s64) = G_SEXT %0
+ %2(s8) = COPY %w0
+ %3(s32) = G_SEXT %2
+ %4(s16) = G_SEXT %2
+...
+
+---
+# CHECK-LABEL: name: other_casts
+name: other_casts
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64all }
+# CHECK-NEXT: - { id: 1, class: fpr64 }
+# CHECK-NEXT: - { id: 2, class: gpr64 }
+# CHECK-NEXT: - { id: 3, class: gpr64 }
+# CHECK-NEXT: - { id: 4, class: gpr32 }
+# CHECK-NEXT: - { id: 5, class: gpr32 }
+# CHECK-NEXT: - { id: 6, class: gpr32 }
+# CHECK-NEXT: - { id: 7, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+ - { id: 2, class: gpr }
+ - { id: 3, class: gpr }
+ - { id: 4, class: gpr }
+ - { id: 5, class: gpr }
+ - { id: 6, class: gpr }
+ - { id: 7, class: gpr }
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %0
+# CHECK: %2 = COPY %0
+# CHECK: %3 = COPY %2
+# CHECK: %4 = COPY %2.sub_32
+# CHECK: %5 = COPY %2.sub_32
+# CHECK: %6 = COPY %2.sub_32
+# CHECK: %7 = COPY %2.sub_32
+body: |
+ bb.0:
+ liveins: %x0
+ %0(s64) = COPY %x0
+ %1(<8 x s8>) = G_BITCAST %0(s64)
+ %2(p0) = G_INTTOPTR %0
+
+ %3(s64) = G_PTRTOINT %2
+ %4(s32) = G_PTRTOINT %2
+ %5(s16) = G_PTRTOINT %2
+ %6(s8) = G_PTRTOINT %2
+ %7(s1) = G_PTRTOINT %2
+...
+
+---
+# CHECK-LABEL: name: bitcast_s32_gpr
+name: bitcast_s32_gpr
+legalized: true
+regBankSelected: true
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32all }
+# CHECK-NEXT: - { id: 1, class: gpr32all }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = COPY %0
+body: |
+ bb.0:
+ liveins: %w0
+
+ %0(s32) = COPY %w0
+ %1(s32) = G_BITCAST %0
+...
+
+---
+# CHECK-LABEL: name: bitcast_s32_fpr
+name: bitcast_s32_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr32 }
+# CHECK-NEXT: - { id: 1, class: fpr32 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %s0
+# CHECK: %1 = COPY %0
+body: |
+ bb.0:
+ liveins: %s0
+
+ %0(s32) = COPY %s0
+ %1(s32) = G_BITCAST %0
+...
+
+---
+# CHECK-LABEL: name: bitcast_s32_gpr_fpr
+name: bitcast_s32_gpr_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32all }
+# CHECK-NEXT: - { id: 1, class: fpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = COPY %0
+body: |
+ bb.0:
+ liveins: %w0
+
+ %0(s32) = COPY %w0
+ %1(s32) = G_BITCAST %0
+...
+
+---
+# CHECK-LABEL: name: bitcast_s32_fpr_gpr
+name: bitcast_s32_fpr_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32all }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %s0
+# CHECK: %1 = COPY %0
+body: |
+ bb.0:
+ liveins: %s0
+
+ %0(s32) = COPY %s0
+ %1(s32) = G_BITCAST %0
+...
+
+---
+# CHECK-LABEL: name: bitcast_s64_gpr
+name: bitcast_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64all }
+# CHECK-NEXT: - { id: 1, class: gpr64all }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %0
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(s64) = COPY %x0
+ %1(s64) = G_BITCAST %0
+...
+
+---
+# CHECK-LABEL: name: bitcast_s64_fpr
+name: bitcast_s64_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr64 }
+# CHECK-NEXT: - { id: 1, class: fpr64 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %d0
+# CHECK: %1 = COPY %0
+body: |
+ bb.0:
+ liveins: %d0
+
+ %0(s64) = COPY %d0
+ %1(s64) = G_BITCAST %0
+...
+
+---
+# CHECK-LABEL: name: bitcast_s64_gpr_fpr
+name: bitcast_s64_gpr_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64all }
+# CHECK-NEXT: - { id: 1, class: fpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %0
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(s64) = COPY %x0
+ %1(s64) = G_BITCAST %0
+...
+
+---
+# CHECK-LABEL: name: bitcast_s64_fpr_gpr
+name: bitcast_s64_fpr_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64all }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %d0
+# CHECK: %1 = COPY %0
+body: |
+ bb.0:
+ liveins: %d0
+
+ %0(s64) = COPY %d0
+ %1(s64) = G_BITCAST %0
+...
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-br.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-br.mir?rev=297856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-br.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-br.mir Wed Mar 15 11:29:37 2017
@@ -0,0 +1,71 @@
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+ define void @unconditional_br() { ret void }
+ define void @conditional_br() { ret void }
+ define void @indirect_br() { ret void }
+...
+
+---
+# CHECK-LABEL: name: unconditional_br
+name: unconditional_br
+legalized: true
+regBankSelected: true
+
+# CHECK: body:
+# CHECK: bb.0:
+# CHECK: successors: %bb.0
+# CHECK: B %bb.0
+body: |
+ bb.0:
+ successors: %bb.0
+
+ G_BR %bb.0
+...
+
+---
+# CHECK-LABEL: name: conditional_br
+name: conditional_br
+legalized: true
+regBankSelected: true
+
+registers:
+ - { id: 0, class: gpr }
+
+# CHECK: body:
+# CHECK: bb.0:
+# CHECK: TBNZW %0, 0, %bb.1
+# CHECK: B %bb.0
+body: |
+ bb.0:
+ successors: %bb.0, %bb.1
+ %0(s1) = COPY %w0
+ G_BRCOND %0(s1), %bb.1
+ G_BR %bb.0
+
+ bb.1:
+...
+
+---
+# CHECK-LABEL: name: indirect_br
+name: indirect_br
+legalized: true
+regBankSelected: true
+
+registers:
+ - { id: 0, class: gpr }
+
+# CHECK: body:
+# CHECK: bb.0:
+# CHECK: %0 = COPY %x0
+# CHECK: BR %0
+body: |
+ bb.0:
+ successors: %bb.0, %bb.1
+ %0(p0) = COPY %x0
+ G_BRINDIRECT %0(p0)
+
+ bb.1:
+...
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-casts.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-casts.mir?rev=297856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-casts.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-casts.mir Wed Mar 15 11:29:37 2017
@@ -0,0 +1,204 @@
+# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+ define void @bitcast_s32_gpr() { ret void }
+ define void @bitcast_s32_fpr() { ret void }
+ define void @bitcast_s32_gpr_fpr() { ret void }
+ define void @bitcast_s32_fpr_gpr() { ret void }
+ define void @bitcast_s64_gpr() { ret void }
+ define void @bitcast_s64_fpr() { ret void }
+ define void @bitcast_s64_gpr_fpr() { ret void }
+ define void @bitcast_s64_fpr_gpr() { ret void }
+...
+
+---
+# CHECK-LABEL: name: bitcast_s32_gpr
+name: bitcast_s32_gpr
+legalized: true
+regBankSelected: true
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32all }
+# CHECK-NEXT: - { id: 1, class: gpr32all }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = COPY %0
+body: |
+ bb.0:
+ liveins: %w0
+
+ %0(s32) = COPY %w0
+ %1(s32) = G_BITCAST %0
+...
+
+---
+# CHECK-LABEL: name: bitcast_s32_fpr
+name: bitcast_s32_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr32 }
+# CHECK-NEXT: - { id: 1, class: fpr32 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %s0
+# CHECK: %1 = COPY %0
+body: |
+ bb.0:
+ liveins: %s0
+
+ %0(s32) = COPY %s0
+ %1(s32) = G_BITCAST %0
+...
+
+---
+# CHECK-LABEL: name: bitcast_s32_gpr_fpr
+name: bitcast_s32_gpr_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32all }
+# CHECK-NEXT: - { id: 1, class: fpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = COPY %0
+body: |
+ bb.0:
+ liveins: %w0
+
+ %0(s32) = COPY %w0
+ %1(s32) = G_BITCAST %0
+...
+
+---
+# CHECK-LABEL: name: bitcast_s32_fpr_gpr
+name: bitcast_s32_fpr_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32all }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %s0
+# CHECK: %1 = COPY %0
+body: |
+ bb.0:
+ liveins: %s0
+
+ %0(s32) = COPY %s0
+ %1(s32) = G_BITCAST %0
+...
+
+---
+# CHECK-LABEL: name: bitcast_s64_gpr
+name: bitcast_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64all }
+# CHECK-NEXT: - { id: 1, class: gpr64all }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %0
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(s64) = COPY %x0
+ %1(s64) = G_BITCAST %0
+...
+
+---
+# CHECK-LABEL: name: bitcast_s64_fpr
+name: bitcast_s64_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr64 }
+# CHECK-NEXT: - { id: 1, class: fpr64 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %d0
+# CHECK: %1 = COPY %0
+body: |
+ bb.0:
+ liveins: %d0
+
+ %0(s64) = COPY %d0
+ %1(s64) = G_BITCAST %0
+...
+
+---
+# CHECK-LABEL: name: bitcast_s64_gpr_fpr
+name: bitcast_s64_gpr_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64all }
+# CHECK-NEXT: - { id: 1, class: fpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %0
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(s64) = COPY %x0
+ %1(s64) = G_BITCAST %0
+...
+
+---
+# CHECK-LABEL: name: bitcast_s64_fpr_gpr
+name: bitcast_s64_fpr_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64all }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %d0
+# CHECK: %1 = COPY %0
+body: |
+ bb.0:
+ liveins: %d0
+
+ %0(s64) = COPY %d0
+ %1(s64) = G_BITCAST %0
+...
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir?rev=297856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir Wed Mar 15 11:29:37 2017
@@ -0,0 +1,460 @@
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+ define void @fptrunc() { ret void }
+ define void @fpext() { ret void }
+
+ define void @sitofp_s32_s32_fpr() { ret void }
+ define void @sitofp_s32_s64_fpr() { ret void }
+ define void @sitofp_s64_s32_fpr() { ret void }
+ define void @sitofp_s64_s64_fpr() { ret void }
+
+ define void @uitofp_s32_s32_fpr() { ret void }
+ define void @uitofp_s32_s64_fpr() { ret void }
+ define void @uitofp_s64_s32_fpr() { ret void }
+ define void @uitofp_s64_s64_fpr() { ret void }
+
+ define void @fptosi_s32_s32_gpr() { ret void }
+ define void @fptosi_s32_s64_gpr() { ret void }
+ define void @fptosi_s64_s32_gpr() { ret void }
+ define void @fptosi_s64_s64_gpr() { ret void }
+
+ define void @fptoui_s32_s32_gpr() { ret void }
+ define void @fptoui_s32_s64_gpr() { ret void }
+ define void @fptoui_s64_s32_gpr() { ret void }
+ define void @fptoui_s64_s64_gpr() { ret void }
+...
+
+---
+# CHECK-LABEL: name: fptrunc
+name: fptrunc
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr64 }
+# CHECK: - { id: 1, class: fpr32 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %d0
+# CHECK: %1 = FCVTSDr %0
+body: |
+ bb.0:
+ liveins: %d0
+
+ %0(s64) = COPY %d0
+ %1(s32) = G_FPTRUNC %0
+...
+
+---
+# CHECK-LABEL: name: fpext
+name: fpext
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK: - { id: 0, class: fpr32 }
+# CHECK: - { id: 1, class: fpr64 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %s0
+# CHECK: %1 = FCVTDSr %0
+body: |
+ bb.0:
+ liveins: %d0
+
+ %0(s32) = COPY %s0
+ %1(s64) = G_FPEXT %0
+...
+
+---
+# CHECK-LABEL: name: sitofp_s32_s32_fpr
+name: sitofp_s32_s32_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: fpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = SCVTFUWSri %0
+body: |
+ bb.0:
+ liveins: %w0
+
+ %0(s32) = COPY %w0
+ %1(s32) = G_SITOFP %0
+...
+
+---
+# CHECK-LABEL: name: sitofp_s32_s64_fpr
+name: sitofp_s32_s64_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: fpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = SCVTFUXSri %0
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(s64) = COPY %x0
+ %1(s32) = G_SITOFP %0
+...
+
+---
+# CHECK-LABEL: name: sitofp_s64_s32_fpr
+name: sitofp_s64_s32_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: fpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = SCVTFUWDri %0
+body: |
+ bb.0:
+ liveins: %w0
+
+ %0(s32) = COPY %w0
+ %1(s64) = G_SITOFP %0
+...
+
+---
+# CHECK-LABEL: name: sitofp_s64_s64_fpr
+name: sitofp_s64_s64_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: fpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = SCVTFUXDri %0
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(s64) = COPY %x0
+ %1(s64) = G_SITOFP %0
+...
+
+---
+# CHECK-LABEL: name: uitofp_s32_s32_fpr
+name: uitofp_s32_s32_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: fpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = UCVTFUWSri %0
+body: |
+ bb.0:
+ liveins: %w0
+
+ %0(s32) = COPY %w0
+ %1(s32) = G_UITOFP %0
+...
+
+---
+# CHECK-LABEL: name: uitofp_s32_s64_fpr
+name: uitofp_s32_s64_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: fpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = UCVTFUXSri %0
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(s64) = COPY %x0
+ %1(s32) = G_UITOFP %0
+...
+
+---
+# CHECK-LABEL: name: uitofp_s64_s32_fpr
+name: uitofp_s64_s32_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: fpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = UCVTFUWDri %0
+body: |
+ bb.0:
+ liveins: %w0
+
+ %0(s32) = COPY %w0
+ %1(s64) = G_UITOFP %0
+...
+
+---
+# CHECK-LABEL: name: uitofp_s64_s64_fpr
+name: uitofp_s64_s64_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: fpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = UCVTFUXDri %0
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(s64) = COPY %x0
+ %1(s64) = G_UITOFP %0
+...
+
+---
+# CHECK-LABEL: name: fptosi_s32_s32_gpr
+name: fptosi_s32_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %s0
+# CHECK: %1 = FCVTZSUWSr %0
+body: |
+ bb.0:
+ liveins: %s0
+
+ %0(s32) = COPY %s0
+ %1(s32) = G_FPTOSI %0
+...
+
+---
+# CHECK-LABEL: name: fptosi_s32_s64_gpr
+name: fptosi_s32_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %d0
+# CHECK: %1 = FCVTZSUWDr %0
+body: |
+ bb.0:
+ liveins: %d0
+
+ %0(s64) = COPY %d0
+ %1(s32) = G_FPTOSI %0
+...
+
+---
+# CHECK-LABEL: name: fptosi_s64_s32_gpr
+name: fptosi_s64_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %s0
+# CHECK: %1 = FCVTZSUXSr %0
+body: |
+ bb.0:
+ liveins: %s0
+
+ %0(s32) = COPY %s0
+ %1(s64) = G_FPTOSI %0
+...
+
+---
+# CHECK-LABEL: name: fptosi_s64_s64_gpr
+name: fptosi_s64_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %d0
+# CHECK: %1 = FCVTZSUXDr %0
+body: |
+ bb.0:
+ liveins: %d0
+
+ %0(s64) = COPY %d0
+ %1(s64) = G_FPTOSI %0
+...
+
+---
+# CHECK-LABEL: name: fptoui_s32_s32_gpr
+name: fptoui_s32_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %s0
+# CHECK: %1 = FCVTZUUWSr %0
+body: |
+ bb.0:
+ liveins: %s0
+
+ %0(s32) = COPY %s0
+ %1(s32) = G_FPTOUI %0
+...
+
+---
+# CHECK-LABEL: name: fptoui_s32_s64_gpr
+name: fptoui_s32_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %d0
+# CHECK: %1 = FCVTZUUWDr %0
+body: |
+ bb.0:
+ liveins: %d0
+
+ %0(s64) = COPY %d0
+ %1(s32) = G_FPTOUI %0
+...
+
+---
+# CHECK-LABEL: name: fptoui_s64_s32_gpr
+name: fptoui_s64_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %s0
+# CHECK: %1 = FCVTZUUXSr %0
+body: |
+ bb.0:
+ liveins: %s0
+
+ %0(s32) = COPY %s0
+ %1(s64) = G_FPTOUI %0
+...
+
+---
+# CHECK-LABEL: name: fptoui_s64_s64_gpr
+name: fptoui_s64_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %d0
+# CHECK: %1 = FCVTZUUXDr %0
+body: |
+ bb.0:
+ liveins: %d0
+
+ %0(s64) = COPY %d0
+ %1(s64) = G_FPTOUI %0
+...
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mir?rev=297856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mir Wed Mar 15 11:29:37 2017
@@ -0,0 +1,214 @@
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+ define void @load_s64_gpr(i64* %addr) { ret void }
+ define void @load_s32_gpr(i32* %addr) { ret void }
+ define void @load_s16_gpr(i16* %addr) { ret void }
+ define void @load_s8_gpr(i8* %addr) { ret void }
+ define void @load_s64_fpr(i64* %addr) { ret void }
+ define void @load_s32_fpr(i32* %addr) { ret void }
+ define void @load_s16_fpr(i16* %addr) { ret void }
+ define void @load_s8_fpr(i8* %addr) { ret void }
+...
+
+---
+# CHECK-LABEL: name: load_s64_gpr
+name: load_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = LDRXui %0, 0 :: (load 8 from %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(p0) = COPY %x0
+ %1(s64) = G_LOAD %0 :: (load 8 from %ir.addr)
+
+...
+
+---
+# CHECK-LABEL: name: load_s32_gpr
+name: load_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = LDRWui %0, 0 :: (load 4 from %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(p0) = COPY %x0
+ %1(s32) = G_LOAD %0 :: (load 4 from %ir.addr)
+
+...
+
+---
+# CHECK-LABEL: name: load_s16_gpr
+name: load_s16_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = LDRHHui %0, 0 :: (load 2 from %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(p0) = COPY %x0
+ %1(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
+
+...
+
+---
+# CHECK-LABEL: name: load_s8_gpr
+name: load_s8_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = LDRBBui %0, 0 :: (load 1 from %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(p0) = COPY %x0
+ %1(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+
+...
+
+---
+# CHECK-LABEL: name: load_s64_fpr
+name: load_s64_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: fpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = LDRDui %0, 0 :: (load 8 from %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(p0) = COPY %x0
+ %1(s64) = G_LOAD %0 :: (load 8 from %ir.addr)
+
+...
+
+---
+# CHECK-LABEL: name: load_s32_fpr
+name: load_s32_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: fpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = LDRSui %0, 0 :: (load 4 from %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(p0) = COPY %x0
+ %1(s32) = G_LOAD %0 :: (load 4 from %ir.addr)
+
+...
+
+---
+# CHECK-LABEL: name: load_s16_fpr
+name: load_s16_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: fpr16 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = LDRHui %0, 0 :: (load 2 from %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(p0) = COPY %x0
+ %1(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
+
+...
+
+---
+# CHECK-LABEL: name: load_s8_fpr
+name: load_s8_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: fpr8 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = LDRBui %0, 0 :: (load 1 from %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(p0) = COPY %x0
+ %1(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+
+...
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-property.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-property.mir?rev=297856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-property.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-property.mir Wed Mar 15 11:29:37 2017
@@ -0,0 +1,21 @@
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+ define void @selected_property() { ret void }
+...
+
+---
+# Check that we set the "selected" property.
+# CHECK-LABEL: name: selected_property
+# CHECK: legalized: true
+# CHECK-NEXT: regBankSelected: true
+# CHECK-NEXT: selected: true
+name: selected_property
+legalized: true
+regBankSelected: true
+selected: false
+body: |
+ bb.0:
+...
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-store.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-store.mir?rev=297856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-store.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-store.mir Wed Mar 15 11:29:37 2017
@@ -0,0 +1,174 @@
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+ define void @store_s64_gpr(i64* %addr) { ret void }
+ define void @store_s32_gpr(i32* %addr) { ret void }
+ define void @store_s16_gpr(i16* %addr) { ret void }
+ define void @store_s8_gpr(i8* %addr) { ret void }
+ define void @store_s64_fpr(i64* %addr) { ret void }
+ define void @store_s32_fpr(i32* %addr) { ret void }
+...
+
+---
+# CHECK-LABEL: name: store_s64_gpr
+name: store_s64_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %x1
+# CHECK: STRXui %1, %0, 0 :: (store 8 into %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0, %x1
+
+ %0(p0) = COPY %x0
+ %1(s64) = COPY %x1
+ G_STORE %1, %0 :: (store 8 into %ir.addr)
+
+...
+
+---
+# CHECK-LABEL: name: store_s32_gpr
+name: store_s32_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %w1
+# CHECK: STRWui %1, %0, 0 :: (store 4 into %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0, %w1
+
+ %0(p0) = COPY %x0
+ %1(s32) = COPY %w1
+ G_STORE %1, %0 :: (store 4 into %ir.addr)
+
+...
+
+---
+# CHECK-LABEL: name: store_s16_gpr
+name: store_s16_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %w1
+# CHECK: STRHHui %1, %0, 0 :: (store 2 into %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0, %w1
+
+ %0(p0) = COPY %x0
+ %1(s16) = COPY %w1
+ G_STORE %1, %0 :: (store 2 into %ir.addr)
+
+...
+
+---
+# CHECK-LABEL: name: store_s8_gpr
+name: store_s8_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %w1
+# CHECK: STRBBui %1, %0, 0 :: (store 1 into %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0, %w1
+
+ %0(p0) = COPY %x0
+ %1(s8) = COPY %w1
+ G_STORE %1, %0 :: (store 1 into %ir.addr)
+
+...
+
+---
+# CHECK-LABEL: name: store_s64_fpr
+name: store_s64_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: fpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %d1
+# CHECK: STRDui %1, %0, 0 :: (store 8 into %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0, %d1
+
+ %0(p0) = COPY %x0
+ %1(s64) = COPY %d1
+ G_STORE %1, %0 :: (store 8 into %ir.addr)
+
+...
+
+---
+# CHECK-LABEL: name: store_s32_fpr
+name: store_s32_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: fpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %s1
+# CHECK: STRSui %1, %0, 0 :: (store 4 into %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0, %s1
+
+ %0(p0) = COPY %x0
+ %1(s32) = COPY %s1
+ G_STORE %1, %0 :: (store 4 into %ir.addr)
+
+...
Copied: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-xor.mir (from r297855, llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect-xor.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-xor.mir?p2=llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-xor.mir&p1=llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect-xor.mir&r1=297855&r2=297856&rev=297856&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect-xor.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-xor.mir Wed Mar 15 11:29:37 2017
@@ -1,9 +1,4 @@
-# RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=IOS
-# RUN: llc -O0 -mtriple=aarch64-linux-gnu -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LINUX-DEFAULT
-# RUN: llc -O0 -mtriple=aarch64-linux-gnu -relocation-model=pic -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LINUX-PIC
-
-# Test the instruction selector.
-# As we support more instructions, we need to split this up.
+# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select.mir?rev=297856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select.mir Wed Mar 15 11:29:37 2017
@@ -0,0 +1,298 @@
+# RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=IOS
+# RUN: llc -O0 -mtriple=aarch64-linux-gnu -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LINUX-DEFAULT
+# RUN: llc -O0 -mtriple=aarch64-linux-gnu -relocation-model=pic -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LINUX-PIC
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+ define void @frame_index() {
+ %ptr0 = alloca i64
+ ret void
+ }
+
+ define i8* @gep(i8* %in) { ret i8* undef }
+
+ define i8* @ptr_mask(i8* %in) { ret i8* undef }
+
+ @var_local = global i8 0
+ define i8* @global_local() { ret i8* undef }
+
+ @var_got = external global i8
+ define i8* @global_got() { ret i8* undef }
+
+ define void @icmp() { ret void }
+ define void @fcmp() { ret void }
+
+ define void @phi() { ret void }
+
+ define void @select() { ret void }
+...
+
+---
+# CHECK-LABEL: name: frame_index
+name: frame_index
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+registers:
+ - { id: 0, class: gpr }
+
+stack:
+ - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
+
+# CHECK: body:
+# CHECK: %0 = ADDXri %stack.0.ptr0, 0, 0
+body: |
+ bb.0:
+ %0(p0) = G_FRAME_INDEX %stack.0.ptr0
+...
+
+---
+# CHECK-LABEL: name: gep
+name: gep
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %1 = MOVi64imm 42
+# CHECK: %2 = ADDXrr %0, %1
+body: |
+ bb.0:
+ liveins: %x0
+ %0(p0) = COPY %x0
+ %1(s64) = G_CONSTANT i64 42
+ %2(p0) = G_GEP %0, %1(s64)
+...
+
+---
+# CHECK-LABEL: name: ptr_mask
+name: ptr_mask
+legalized: true
+regBankSelected: true
+
+# CHECK: body:
+# CHECK: %1 = ANDXri %0, 8060
+body: |
+ bb.0:
+ liveins: %x0
+ %0:gpr(p0) = COPY %x0
+ %1:gpr(p0) = G_PTR_MASK %0, 3
+...
+
+---
+# Global defined in the same linkage unit so no GOT is needed
+# CHECK-LABEL: name: global_local
+name: global_local
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: gpr }
+
+# CHECK: body:
+# IOS: %0 = MOVaddr target-flags(aarch64-page) @var_local, target-flags(aarch64-pageoff, aarch64-nc) @var_local
+# LINUX-DEFAULT: %0 = MOVaddr target-flags(aarch64-page) @var_local, target-flags(aarch64-pageoff, aarch64-nc) @var_local
+# LINUX-PIC: %0 = LOADgot target-flags(aarch64-got) @var_local
+body: |
+ bb.0:
+ %0(p0) = G_GLOBAL_VALUE @var_local
+...
+
+---
+# CHECK-LABEL: name: global_got
+name: global_got
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: gpr }
+
+# CHECK: body:
+# IOS: %0 = LOADgot target-flags(aarch64-got) @var_got
+# LINUX-DEFAULT: %0 = MOVaddr target-flags(aarch64-page) @var_got, target-flags(aarch64-pageoff, aarch64-nc) @var_got
+# LINUX-PIC: %0 = LOADgot target-flags(aarch64-got) @var_got
+body: |
+ bb.0:
+ %0(p0) = G_GLOBAL_VALUE @var_got
+...
+
+---
+# CHECK-LABEL: name: icmp
+name: icmp
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr64 }
+# CHECK-NEXT: - { id: 3, class: gpr32 }
+# CHECK-NEXT: - { id: 4, class: gpr64 }
+# CHECK-NEXT: - { id: 5, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+ - { id: 3, class: gpr }
+ - { id: 4, class: gpr }
+ - { id: 5, class: gpr }
+
+# CHECK: body:
+# CHECK: %wzr = SUBSWrr %0, %0, implicit-def %nzcv
+# CHECK: %1 = CSINCWr %wzr, %wzr, 1, implicit %nzcv
+
+# CHECK: %xzr = SUBSXrr %2, %2, implicit-def %nzcv
+# CHECK: %3 = CSINCWr %wzr, %wzr, 3, implicit %nzcv
+
+# CHECK: %xzr = SUBSXrr %4, %4, implicit-def %nzcv
+# CHECK: %5 = CSINCWr %wzr, %wzr, 0, implicit %nzcv
+
+body: |
+ bb.0:
+ liveins: %w0, %x0
+
+ %0(s32) = COPY %w0
+ %1(s1) = G_ICMP intpred(eq), %0, %0
+
+ %2(s64) = COPY %x0
+ %3(s1) = G_ICMP intpred(uge), %2, %2
+
+ %4(p0) = COPY %x0
+ %5(s1) = G_ICMP intpred(ne), %4, %4
+...
+
+---
+# CHECK-LABEL: name: fcmp
+name: fcmp
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: fpr64 }
+# CHECK-NEXT: - { id: 3, class: gpr32 }
+# CHECK-NEXT: - { id: 4, class: gpr32 }
+# CHECK-NEXT: - { id: 5, class: gpr32 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: fpr }
+ - { id: 3, class: gpr }
+
+# CHECK: body:
+# CHECK: FCMPSrr %0, %0, implicit-def %nzcv
+# CHECK: [[TST_MI:%[0-9]+]] = CSINCWr %wzr, %wzr, 5, implicit %nzcv
+# CHECK: [[TST_GT:%[0-9]+]] = CSINCWr %wzr, %wzr, 13, implicit %nzcv
+# CHECK: %1 = ORRWrr [[TST_MI]], [[TST_GT]]
+
+# CHECK: FCMPDrr %2, %2, implicit-def %nzcv
+# CHECK: %3 = CSINCWr %wzr, %wzr, 4, implicit %nzcv
+
+body: |
+ bb.0:
+ liveins: %w0, %x0
+
+ %0(s32) = COPY %s0
+ %1(s1) = G_FCMP floatpred(one), %0, %0
+
+ %2(s64) = COPY %d0
+ %3(s1) = G_FCMP floatpred(uge), %2, %2
+
+...
+
+---
+# CHECK-LABEL: name: phi
+name: phi
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: fpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: fpr32 }
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: fpr }
+
+# CHECK: body:
+# CHECK: bb.1:
+# CHECK: %2 = PHI %0, %bb.0, %2, %bb.1
+
+body: |
+ bb.0:
+ liveins: %s0, %w0
+ successors: %bb.1
+ %0(s32) = COPY %s0
+ %1(s1) = COPY %w0
+
+ bb.1:
+ successors: %bb.1, %bb.2
+ %2(s32) = PHI %0, %bb.0, %2, %bb.1
+ G_BRCOND %1, %bb.1
+
+ bb.2:
+ %s0 = COPY %2
+ RET_ReallyLR implicit %s0
+...
+
+---
+# CHECK-LABEL: name: select
+name: select
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr32 }
+# CHECK-NEXT: - { id: 3, class: gpr32 }
+# CHECK-NEXT: - { id: 4, class: gpr64 }
+# CHECK-NEXT: - { id: 5, class: gpr64 }
+# CHECK-NEXT: - { id: 6, class: gpr64 }
+# CHECK-NEXT: - { id: 7, class: gpr64 }
+# CHECK-NEXT: - { id: 8, class: gpr64 }
+# CHECK-NEXT: - { id: 9, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+ - { id: 3, class: gpr }
+ - { id: 4, class: gpr }
+ - { id: 5, class: gpr }
+ - { id: 6, class: gpr }
+ - { id: 7, class: gpr }
+ - { id: 8, class: gpr }
+ - { id: 9, class: gpr }
+
+# CHECK: body:
+# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv
+# CHECK: %3 = CSELWr %1, %2, 1, implicit %nzcv
+# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv
+# CHECK: %6 = CSELXr %4, %5, 1, implicit %nzcv
+# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv
+# CHECK: %9 = CSELXr %7, %8, 1, implicit %nzcv
+body: |
+ bb.0:
+ liveins: %w0, %w1, %w2
+ %0(s1) = COPY %w0
+
+ %1(s32) = COPY %w1
+ %2(s32) = COPY %w2
+ %3(s32) = G_SELECT %0, %1, %2
+
+ %4(s64) = COPY %x0
+ %5(s64) = COPY %x1
+ %6(s64) = G_SELECT %0, %4, %5
+
+ %7(p0) = COPY %x0
+ %8(p0) = COPY %x1
+ %9(p0) = G_SELECT %0, %7, %8
+...
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