[llvm] r297833 - [X86][SSE] Fixed shuffle MOVSS/MOVSD combining of all zeroable inputs

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Wed Mar 15 08:16:46 2017
New Revision: 297833

URL: http://llvm.org/viewvc/llvm-project?rev=297833&view=rev
Log:
[X86][SSE] Fixed shuffle MOVSS/MOVSD combining of all zeroable inputs

Turns out it can happen, so the assertion was too harsh

Found during fuzz testing

Added:
    llvm/trunk/test/CodeGen/X86/shuffle-combine-crash-2.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=297833&r1=297832&r2=297833&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Mar 15 08:16:46 2017
@@ -28221,19 +28221,20 @@ static SDValue combineTargetShuffle(SDVa
   }
   case X86ISD::MOVSD:
   case X86ISD::MOVSS: {
-    bool isFloat = VT.isFloatingPoint();
     SDValue V0 = peekThroughBitcasts(N->getOperand(0));
     SDValue V1 = peekThroughBitcasts(N->getOperand(1));
-    bool isFloat0 = V0.getSimpleValueType().isFloatingPoint();
-    bool isFloat1 = V1.getSimpleValueType().isFloatingPoint();
     bool isZero0 = ISD::isBuildVectorAllZeros(V0.getNode());
     bool isZero1 = ISD::isBuildVectorAllZeros(V1.getNode());
-    assert(!(isZero0 && isZero1) && "Zeroable shuffle detected.");
+    if (isZero0 && isZero1)
+      return SDValue();
 
     // We often lower to MOVSD/MOVSS from integer as well as native float
     // types; remove unnecessary domain-crossing bitcasts if we can to make it
     // easier to combine shuffles later on. We've already accounted for the
     // domain switching cost when we decided to lower with it.
+    bool isFloat = VT.isFloatingPoint();
+    bool isFloat0 = V0.getSimpleValueType().isFloatingPoint();
+    bool isFloat1 = V1.getSimpleValueType().isFloatingPoint();
     if ((isFloat != isFloat0 || isZero0) && (isFloat != isFloat1 || isZero1)) {
       MVT NewVT = isFloat ? (X86ISD::MOVSD == Opcode ? MVT::v2i64 : MVT::v4i32)
                           : (X86ISD::MOVSD == Opcode ? MVT::v2f64 : MVT::v4f32);

Added: llvm/trunk/test/CodeGen/X86/shuffle-combine-crash-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shuffle-combine-crash-2.ll?rev=297833&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/shuffle-combine-crash-2.ll (added)
+++ llvm/trunk/test/CodeGen/X86/shuffle-combine-crash-2.ll Wed Mar 15 08:16:46 2017
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
+
+define <4 x i64> @fold_movsd_zero() {
+; X86-LABEL: fold_movsd_zero:
+; X86:       # BB#0:
+; X86-NEXT:    xorps %xmm0, %xmm0
+; X86-NEXT:    xorps %xmm1, %xmm1
+; X86-NEXT:    retl
+;
+; X64-LABEL: fold_movsd_zero:
+; X64:       # BB#0:
+; X64-NEXT:    xorps %xmm0, %xmm0
+; X64-NEXT:    xorps %xmm1, %xmm1
+; X64-NEXT:    retq
+  %insert = insertelement <4 x i64> zeroinitializer, i64 0, i32 0
+  %shuffle = shufflevector <4 x i64> %insert, <4 x i64> zeroinitializer, <4 x i32> <i32 3, i32 5, i32 7, i32 1>
+  ret <4 x i64> %shuffle
+}