[llvm] r297707 - [AVX-512] Use iPTR instead of i64 in patterns for extract_subvector/insert_subvector index.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 13 23:40:04 PDT 2017
Author: ctopper
Date: Tue Mar 14 01:40:04 2017
New Revision: 297707
URL: http://llvm.org/viewvc/llvm-project?rev=297707&view=rev
Log:
[AVX-512] Use iPTR instead of i64 in patterns for extract_subvector/insert_subvector index.
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/test/CodeGen/X86/avx512-load-store.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=297707&r1=297706&r2=297707&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Tue Mar 14 01:40:04 2017
@@ -3303,8 +3303,8 @@ def : Pat<(masked_store addr:$dst, Mask,
(_.info512.VT (insert_subvector undef,
(_.info256.VT (insert_subvector undef,
(_.info128.VT _.info128.RC:$src),
- (i64 0))),
- (i64 0)))),
+ (iPTR 0))),
+ (iPTR 0)))),
(!cast<Instruction>(InstrStr#mrk) addr:$dst,
(i1 (COPY_TO_REGCLASS MaskRC:$mask, VK1WM)),
(COPY_TO_REGCLASS _.info128.RC:$src, _.info128.FRC))>;
@@ -3318,7 +3318,7 @@ def : Pat<(_.info128.VT (extract_subvect
(_.info512.VT (masked_load addr:$srcAddr, Mask,
(_.info512.VT (bitconvert
(v16i32 immAllZerosV))))),
- (i64 0))),
+ (iPTR 0))),
(!cast<Instruction>(InstrStr#rmkz)
(i1 (COPY_TO_REGCLASS MaskRC:$mask, VK1WM)),
addr:$srcAddr)>;
@@ -3328,9 +3328,9 @@ def : Pat<(_.info128.VT (extract_subvect
(_.info512.VT (insert_subvector undef,
(_.info256.VT (insert_subvector undef,
(_.info128.VT (X86vzmovl _.info128.RC:$src)),
- (i64 0))),
- (i64 0))))),
- (i64 0))),
+ (iPTR 0))),
+ (iPTR 0))))),
+ (iPTR 0))),
(!cast<Instruction>(InstrStr#rmk) _.info128.RC:$src,
(i1 (COPY_TO_REGCLASS MaskRC:$mask, VK1WM)),
addr:$srcAddr)>;
Modified: llvm/trunk/test/CodeGen/X86/avx512-load-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-load-store.ll?rev=297707&r1=297706&r2=297707&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-load-store.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-load-store.ll Tue Mar 14 01:40:04 2017
@@ -111,13 +111,10 @@ define void @test_mm_mask_store_ss(float
;
; CHECK32-LABEL: test_mm_mask_store_ss:
; CHECK32: # BB#0: # %entry
-; CHECK32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
-; CHECK32-NEXT: andl $1, %ecx
; CHECK32-NEXT: kmovw %ecx, %k1
-; CHECK32-NEXT: vmovups %zmm0, (%eax) {%k1}
-; CHECK32-NEXT: vzeroupper
+; CHECK32-NEXT: vmovss %xmm0, (%eax) {%k1}
; CHECK32-NEXT: retl
entry:
%0 = bitcast float* %__W to <16 x float>*
@@ -138,13 +135,10 @@ define void @test_mm_mask_store_sd(doubl
;
; CHECK32-LABEL: test_mm_mask_store_sd:
; CHECK32: # BB#0: # %entry
-; CHECK32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %cl
-; CHECK32-NEXT: andb $1, %cl
; CHECK32-NEXT: kmovw %ecx, %k1
-; CHECK32-NEXT: vmovupd %zmm0, (%eax) {%k1}
-; CHECK32-NEXT: vzeroupper
+; CHECK32-NEXT: vmovsd %xmm0, (%eax) {%k1}
; CHECK32-NEXT: retl
entry:
%0 = bitcast double* %__W to <8 x double>*
@@ -166,13 +160,8 @@ define <4 x float> @test_mm_mask_load_ss
; CHECK32: # BB#0: # %entry
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
-; CHECK32-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; CHECK32-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
-; CHECK32-NEXT: andl $1, %ecx
-; CHECK32-NEXT: kmovw %ecx, %k1
-; CHECK32-NEXT: vmovups (%eax), %zmm0 {%k1}
-; CHECK32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
-; CHECK32-NEXT: vzeroupper
+; CHECK32-NEXT: kmovw %ecx, %k1
+; CHECK32-NEXT: vmovss (%eax), %xmm0 {%k1}
; CHECK32-NEXT: retl
entry:
%shuffle.i = shufflevector <4 x float> %__A, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 4>
@@ -197,12 +186,8 @@ define <2 x double> @test_mm_mask_load_s
; CHECK32: # BB#0: # %entry
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %cl
-; CHECK32-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
-; CHECK32-NEXT: andb $1, %cl
; CHECK32-NEXT: kmovw %ecx, %k1
-; CHECK32-NEXT: vmovupd (%eax), %zmm0 {%k1}
-; CHECK32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
-; CHECK32-NEXT: vzeroupper
+; CHECK32-NEXT: vmovsd (%eax), %xmm0 {%k1}
; CHECK32-NEXT: retl
entry:
%shuffle5.i = insertelement <2 x double> %__A, double 0.000000e+00, i32 1
@@ -226,11 +211,8 @@ define <4 x float> @test_mm_maskz_load_s
; CHECK32: # BB#0: # %entry
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
-; CHECK32-NEXT: andl $1, %ecx
; CHECK32-NEXT: kmovw %ecx, %k1
-; CHECK32-NEXT: vmovups (%eax), %zmm0 {%k1} {z}
-; CHECK32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
-; CHECK32-NEXT: vzeroupper
+; CHECK32-NEXT: vmovss (%eax), %xmm0 {%k1} {z}
; CHECK32-NEXT: retl
entry:
%0 = bitcast float* %__W to <16 x float>*
@@ -253,11 +235,8 @@ define <2 x double> @test_mm_maskz_load_
; CHECK32: # BB#0: # %entry
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %cl
-; CHECK32-NEXT: andb $1, %cl
; CHECK32-NEXT: kmovw %ecx, %k1
-; CHECK32-NEXT: vmovupd (%eax), %zmm0 {%k1} {z}
-; CHECK32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
-; CHECK32-NEXT: vzeroupper
+; CHECK32-NEXT: vmovsd (%eax), %xmm0 {%k1} {z}
; CHECK32-NEXT: retl
entry:
%0 = bitcast double* %__W to <8 x double>*
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