[llvm] r297621 - [ARM] GlobalISel: Support SP in regbankselect

[Diana Picus via llvm-commits]

Author: rovka
Date: Mon Mar 13 09:28:34 2017
New Revision: 297621

URL: http://llvm.org/viewvc/llvm-project?rev=297621&view=rev
Log:
[ARM] GlobalISel: Support SP in regbankselect

We used to hit an unreachable in getRegBankFromRegClass when dealing with the
stack pointer. This commit adds support for the GPRsp reg class.

Modified:
    llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
    llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=297621&r1=297620&r2=297621&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Mon Mar 13 09:28:34 2017
@@ -180,6 +180,7 @@ const RegisterBank &ARMRegisterBankInfo:
   switch (RC.getID()) {
   case GPRRegClassID:
   case GPRnopcRegClassID:
+  case GPRspRegClassID:
   case tGPR_and_tcGPRRegClassID:
   case tGPRRegClassID:
     return getRegBank(ARM::GPRRegBankID);

Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=297621&r1=297620&r2=297621&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Mon Mar 13 09:28:34 2017
@@ -8,6 +8,8 @@
   define void @test_loads() #0 { ret void }
   define void @test_stores() #0 { ret void }
 
+  define void @test_stack() { ret void }
+
   define void @test_gep() { ret void }
 
   define void @test_constants() { ret void }
@@ -202,6 +204,39 @@ body:             |
 
 ...
 ---
+name:            test_stack
+# CHECK-LABEL: name: test_stack
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb }
+# CHECK: - { id: 1, class: gprb }
+# CHECK: - { id: 2, class: gprb }
+# CHECK: - { id: 3, class: gprb }
+# CHECK: - { id: 4, class: gprb }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+fixedStack:
+  - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
+body:             |
+  bb.0:
+    %0(p0) = G_FRAME_INDEX %fixed-stack.0
+    %1(s32) = G_LOAD %0(p0) :: (load 4 from %fixed-stack.0, align 0)
+
+    %2(p0) = COPY %sp
+    %3(s32) = G_CONSTANT i32 8
+    %4(p0) = G_GEP %2, %3(s32)
+    G_STORE %1(s32), %4(p0) :: (store 4)
+
+    BX_RET 14, _
+
+...
+---
 name:            test_gep
 # CHECK-LABEL: name: test_gep
 legalized:       true