[PATCH] D30529: [GlobalISel] Enable specifying how to legalize non-power-of-2 size types.

[Renato Golin via Phabricator via llvm-commits]

rengolin added a comment.

In https://reviews.llvm.org/D30529#699110, @kristof.beyls wrote:

>   setAction({G_REM, LLT:scalar(1)},
>             {{1, WidenScalar},  // bit sizes [ 1, 31[
>              {32, Lower},       // bit sizes [32, 33[
>              {33, NarrowScalar}, // bit sizes [33, 63[
>              {64, Libcall}, // bit sizes [64, 65[
>              {65, Unsupported} // bit sizes [65, +inf[
>             });
>


I'd expect 33~63 to Widen+LibCall here.

> I hope the above makes sense?

It does, but there are two issues here:

1. How would this inter-operate with table-gen?

IIUC, the idea is to move as much as possible to table-gen. Currently (SelDAG), instructions that are described in table-gen are "legal". It would be good to re-use as much as possible of that, to avoid table-gen bloat.

Are we going to ignore that info and re-build a specific lowering database? Or re-use that for the lowering (thus needing merge, see below)? Or is this technique only for when the generic instruction doesn't map to anything in table-gen?

2. Would this allow merging data?

When sub-arch specific decisions are concerned, having a way to override a base default case would reduce the amount of code on both table-gen and c++ parts.

For example, we could have a default catch-all case like ```{1,widen; 32,legal; 33,unsupp}```, and later on, based on sub-arch decisions, increment legality, lib calls, etc.

cheers,
--renato


https://reviews.llvm.org/D30529