[llvm] r297514 - LTO: Hash type identifier resolutions for WholeProgramDevirt.
Peter Collingbourne via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 10 13:37:11 PST 2017
Author: pcc
Date: Fri Mar 10 15:37:10 2017
New Revision: 297514
URL: http://llvm.org/viewvc/llvm-project?rev=297514&view=rev
Log:
LTO: Hash type identifier resolutions for WholeProgramDevirt.
Differential Revision: https://reviews.llvm.org/D30555
Added:
llvm/trunk/test/ThinLTO/X86/Inputs/cache-typeid-resolutions2.ll
llvm/trunk/test/ThinLTO/X86/Inputs/cache-typeid-resolutions3.ll
Modified:
llvm/trunk/lib/LTO/LTO.cpp
llvm/trunk/test/ThinLTO/X86/Inputs/cache-typeid-resolutions-import.ll
llvm/trunk/test/ThinLTO/X86/cache-typeid-resolutions.ll
Modified: llvm/trunk/lib/LTO/LTO.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/LTO/LTO.cpp?rev=297514&r1=297513&r2=297514&view=diff
==============================================================================
--- llvm/trunk/lib/LTO/LTO.cpp (original)
+++ llvm/trunk/lib/LTO/LTO.cpp Fri Mar 10 15:37:10 2017
@@ -189,6 +189,22 @@ static void computeCacheKey(
AddUnsigned(S.TTRes.TheKind);
AddUnsigned(S.TTRes.SizeM1BitWidth);
+
+ AddUint64(S.WPDRes.size());
+ for (auto &WPD : S.WPDRes) {
+ AddUnsigned(WPD.first);
+ AddUnsigned(WPD.second.TheKind);
+ AddString(WPD.second.SingleImplName);
+
+ AddUint64(WPD.second.ResByArg.size());
+ for (auto &ByArg : WPD.second.ResByArg) {
+ AddUint64(ByArg.first.size());
+ for (uint64_t Arg : ByArg.first)
+ AddUint64(Arg);
+ AddUnsigned(ByArg.second.TheKind);
+ AddUint64(ByArg.second.Info);
+ }
+ }
};
// Include the hash for all type identifiers used by this module.
Modified: llvm/trunk/test/ThinLTO/X86/Inputs/cache-typeid-resolutions-import.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ThinLTO/X86/Inputs/cache-typeid-resolutions-import.ll?rev=297514&r1=297513&r2=297514&view=diff
==============================================================================
--- llvm/trunk/test/ThinLTO/X86/Inputs/cache-typeid-resolutions-import.ll (original)
+++ llvm/trunk/test/ThinLTO/X86/Inputs/cache-typeid-resolutions-import.ll Fri Mar 10 15:37:10 2017
@@ -6,4 +6,10 @@ define i1 @importf1(i8* %p) {
ret i1 %x
}
+define i1 @importf2(i8* %p) {
+ %x = call i1 @f2(i8* %p)
+ ret i1 %x
+}
+
declare i1 @f1(i8* %p)
+declare i1 @f2(i8* %p)
Added: llvm/trunk/test/ThinLTO/X86/Inputs/cache-typeid-resolutions2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ThinLTO/X86/Inputs/cache-typeid-resolutions2.ll?rev=297514&view=auto
==============================================================================
--- llvm/trunk/test/ThinLTO/X86/Inputs/cache-typeid-resolutions2.ll (added)
+++ llvm/trunk/test/ThinLTO/X86/Inputs/cache-typeid-resolutions2.ll Fri Mar 10 15:37:10 2017
@@ -0,0 +1,10 @@
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+ at vt2 = constant i1 (i8*)* @vf2, !type !0
+
+define internal i1 @vf2(i8* %this) {
+ ret i1 0
+}
+
+!0 = !{i32 0, !"typeid2"}
Added: llvm/trunk/test/ThinLTO/X86/Inputs/cache-typeid-resolutions3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ThinLTO/X86/Inputs/cache-typeid-resolutions3.ll?rev=297514&view=auto
==============================================================================
--- llvm/trunk/test/ThinLTO/X86/Inputs/cache-typeid-resolutions3.ll (added)
+++ llvm/trunk/test/ThinLTO/X86/Inputs/cache-typeid-resolutions3.ll Fri Mar 10 15:37:10 2017
@@ -0,0 +1,15 @@
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+ at vt2a = constant i1 (i8*)* @vf2a, !type !0
+ at vt2b = constant i1 (i8*)* @vf2b, !type !0
+
+define internal i1 @vf2a(i8* %this) {
+ ret i1 0
+}
+
+define internal i1 @vf2b(i8* %this) {
+ ret i1 1
+}
+
+!0 = !{i32 0, !"typeid2"}
Modified: llvm/trunk/test/ThinLTO/X86/cache-typeid-resolutions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ThinLTO/X86/cache-typeid-resolutions.ll?rev=297514&r1=297513&r2=297514&view=diff
==============================================================================
--- llvm/trunk/test/ThinLTO/X86/cache-typeid-resolutions.ll (original)
+++ llvm/trunk/test/ThinLTO/X86/cache-typeid-resolutions.ll Fri Mar 10 15:37:10 2017
@@ -2,15 +2,26 @@
; RUN: opt -module-hash -module-summary %S/Inputs/cache-typeid-resolutions-import.ll -o %t-import.bc
; RUN: llvm-as -o %t1.bc %S/Inputs/cache-typeid-resolutions1.ll
+; RUN: llvm-as -o %t2.bc %S/Inputs/cache-typeid-resolutions2.ll
+; RUN: llvm-as -o %t3.bc %S/Inputs/cache-typeid-resolutions3.ll
; Two resolutions for typeid1: Unsat, Single
; where both t and t-import are sensitive to typeid1's resolution
; so 4 distinct objects in total.
; RUN: rm -rf %t.cache
-; RUN: llvm-lto2 -o %t.o %t.bc %t-import.bc -cache-dir %t.cache -r=%t.bc,f1,plx -r=%t-import.bc,importf1,plx -r=%t-import.bc,f1,lx
-; RUN: llvm-lto2 -o %t.o %t.bc %t-import.bc %t1.bc -cache-dir %t.cache -r=%t.bc,f1,plx -r=%t-import.bc,importf1,plx -r=%t-import.bc,f1,lx -r=%t1.bc,vt1,plx
+; RUN: llvm-lto2 -o %t.o %t.bc %t-import.bc -cache-dir %t.cache -r=%t.bc,f1,plx -r=%t.bc,f2,plx -r=%t-import.bc,importf1,plx -r=%t-import.bc,f1,lx -r=%t-import.bc,importf2,plx -r=%t-import.bc,f2,lx
+; RUN: llvm-lto2 -o %t.o %t.bc %t-import.bc %t1.bc -cache-dir %t.cache -r=%t.bc,f1,plx -r=%t.bc,f2,plx -r=%t-import.bc,importf1,plx -r=%t-import.bc,f1,lx -r=%t-import.bc,importf2,plx -r=%t-import.bc,f2,lx -r=%t1.bc,vt1,plx
; RUN: ls %t.cache | count 4
+; Three resolutions for typeid2: Indir, SingleImpl, UniqueRetVal
+; where both t and t-import are sensitive to typeid2's resolution
+; so 6 distinct objects in total.
+; RUN: rm -rf %t.cache
+; RUN: llvm-lto2 -o %t.o %t.bc %t-import.bc -cache-dir %t.cache -r=%t.bc,f1,plx -r=%t.bc,f2,plx -r=%t-import.bc,importf1,plx -r=%t-import.bc,f1,lx -r=%t-import.bc,importf2,plx -r=%t-import.bc,f2,lx
+; RUN: llvm-lto2 -o %t.o %t.bc %t-import.bc %t2.bc -cache-dir %t.cache -r=%t.bc,f1,plx -r=%t.bc,f2,plx -r=%t2.bc,vt2,plx -r=%t-import.bc,importf1,plx -r=%t-import.bc,f1,lx -r=%t-import.bc,importf2,plx -r=%t-import.bc,f2,lx
+; RUN: llvm-lto2 -o %t.o %t.bc %t-import.bc %t3.bc -cache-dir %t.cache -r=%t.bc,f1,plx -r=%t.bc,f2,plx -r=%t3.bc,vt2a,plx -r=%t3.bc,vt2b,plx -r=%t-import.bc,importf1,plx -r=%t-import.bc,f1,lx -r=%t-import.bc,importf2,plx -r=%t-import.bc,f2,lx
+; RUN: ls %t.cache | count 6
+
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
@@ -19,4 +30,18 @@ define i1 @f1(i8* %p) {
ret i1 %x
}
+define i1 @f2(i8* %obj) {
+ %vtableptr = bitcast i8* %obj to [3 x i8*]**
+ %vtable = load [3 x i8*]*, [3 x i8*]** %vtableptr
+ %vtablei8 = bitcast [3 x i8*]* %vtable to i8*
+ %p = call i1 @llvm.type.test(i8* %vtablei8, metadata !"typeid2")
+ call void @llvm.assume(i1 %p)
+ %fptrptr = getelementptr [3 x i8*], [3 x i8*]* %vtable, i32 0, i32 0
+ %fptr = load i8*, i8** %fptrptr
+ %fptr_casted = bitcast i8* %fptr to i1 (i8*)*
+ %result = call i1 %fptr_casted(i8* %obj)
+ ret i1 %result
+}
+
declare i1 @llvm.type.test(i8*, metadata)
+declare void @llvm.assume(i1)
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