[llvm] r297433 - [x86] add tests for vec div/rem with 0 element in divisor; NFC

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Thu Mar  9 18:55:29 2017
New Revision: 297433

URL: http://llvm.org/viewvc/llvm-project?rev=297433&view=rev
Log:
[x86] add tests for vec div/rem with 0 element in divisor; NFC

Modified:
    llvm/trunk/test/CodeGen/X86/div-rem-simplify.ll

Modified: llvm/trunk/test/CodeGen/X86/div-rem-simplify.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/div-rem-simplify.ll?rev=297433&r1=297432&r2=297433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/div-rem-simplify.ll (original)
+++ llvm/trunk/test/CodeGen/X86/div-rem-simplify.ll Thu Mar  9 18:55:29 2017
@@ -147,3 +147,46 @@ define <4 x i32> @sel_sdiv0_vec(i1 %cond
   ret <4 x i32> %div
 }
 
+; If any element of a constant divisor vector is zero, the whole op is undef.
+
+define <4 x i32> @sdiv0elt_vec(<4 x i32> %x) {
+; CHECK-LABEL: sdiv0elt_vec:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movaps {{.*#+}} xmm0 = <u,12,u,4294967292>
+; CHECK-NEXT:    retq
+  %zero = and <4 x i32> %x, <i32 0, i32 0, i32 0, i32 0>
+  %some_ones = or <4 x i32> %zero, <i32 0, i32 -1, i32 0, i32 3>
+  %div = sdiv <4 x i32> <i32 -11, i32 -12, i32 -13, i32 -14>, %some_ones
+  ret <4 x i32> %div
+}
+
+define <4 x i32> @udiv0elt_vec(<4 x i32> %x) {
+; CHECK-LABEL: udiv0elt_vec:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movaps {{.*#+}} xmm0 = <u,4,3,u>
+; CHECK-NEXT:    retq
+  %div = udiv <4 x i32> <i32 11, i32 12, i32 13, i32 14>, <i32 0, i32 3, i32 4, i32 0>
+  ret <4 x i32> %div
+}
+
+define <4 x i32> @urem0elt_vec(<4 x i32> %x) {
+; CHECK-LABEL: urem0elt_vec:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movaps {{.*#+}} xmm0 = <u,u,u,2>
+; CHECK-NEXT:    retq
+  %zero = and <4 x i32> %x, <i32 0, i32 0, i32 0, i32 0>
+  %some_ones = or <4 x i32> %zero, <i32 0, i32 0, i32 0, i32 3>
+  %rem = urem <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %some_ones
+  ret <4 x i32> %rem
+}
+
+define <4 x i32> @srem0elt_vec(<4 x i32> %x) {
+; CHECK-LABEL: srem0elt_vec:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl $-2, %eax
+; CHECK-NEXT:    movd %eax, %xmm0
+; CHECK-NEXT:    retq
+  %rem = srem <4 x i32> <i32 -11, i32 -12, i32 -13, i32 -14>, <i32 -3, i32 -3, i32 0, i32 2>
+  ret <4 x i32> %rem
+}
+