[PATCH] D30400: For Thumb1, lower ADDC/ADDE/SUBC/SUBE via the glueless ARMISD nodes, same as already done for ARM and Thumb2.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Hmm... given that you've done most of the work of fixing AdjustInstrPostInstrSelection, how hard would it be to add tADCS/tSBCS pseudo-instructions and send them through AdjustInstrPostInstrSelection, as opposed to using custom selection code in C++?   I'm sort of concerned you could run into the same scheduling problem for 128-bit addition.


https://reviews.llvm.org/D30400