[llvm] r297288 - [Hexagon] Use correct offset when extracting from the high word
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 8 07:46:29 PST 2017
Author: kparzysz
Date: Wed Mar 8 09:46:28 2017
New Revision: 297288
URL: http://llvm.org/viewvc/llvm-project?rev=297288&view=rev
Log:
[Hexagon] Use correct offset when extracting from the high word
When extracting a bitfield from the high register in a register pair,
the final offset should be relative to the high register (for 32-bit
extracts).
Added:
llvm/trunk/test/CodeGen/Hexagon/bit-extract-off.ll
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp?rev=297288&r1=297287&r2=297288&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp Wed Mar 8 09:46:28 2017
@@ -2480,6 +2480,7 @@ bool BitSimplification::simplifyExtractL
continue;
if (RW != SW)
SR = (Off/RW == 0) ? Hexagon::isub_lo : Hexagon::isub_hi;
+ Off = Off % RW;
if (!validateReg({R,SR}, ExtOpc, 1))
continue;
Added: llvm/trunk/test/CodeGen/Hexagon/bit-extract-off.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-extract-off.ll?rev=297288&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/bit-extract-off.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/bit-extract-off.ll Wed Mar 8 09:46:28 2017
@@ -0,0 +1,23 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: extractu(r1,#31,#0)
+
+; In the IR this was an extract of 31 bits starting at position 32 in r1:0.
+; When mapping it to an extract from r1, the offset was not reset to 0, and
+; we had "extractu(r1,#31,#32)".
+
+target triple = "hexagon"
+
+define hidden i32 @fred([101 x double]* %a0, i32 %a1, i32* %a2, i32* %a3) #0 {
+b4:
+ br label %b5
+
+b5: ; preds = %b5, %b4
+ %v6 = call double @fabs(double undef) #1
+ store double %v6, double* undef, align 8
+ br label %b5
+}
+
+declare double @fabs(double) #1
+
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }
+attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }
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