[PATCH] D22025: AMDGPU/SI: Do not insert EndCf in an unreachable block

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL297243: AMDGPU/SI: Do not insert EndCf in an unreachable block (authored by chfang).

Changed prior to commit:
  https://reviews.llvm.org/D22025?vs=64790&id=90954#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D22025

Files:
  llvm/trunk/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
  llvm/trunk/test/CodeGen/AMDGPU/ret_jump.ll
  llvm/trunk/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll


Index: llvm/trunk/test/CodeGen/AMDGPU/ret_jump.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/ret_jump.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/ret_jump.ll
@@ -15,7 +15,6 @@
 ; GCN-NEXT: s_branch [[FINAL_BB:BB[0-9]+_[0-9]+]]
 
 ; GCN-NEXT: [[UNREACHABLE_BB]]:
-; GCN-NEXT: s_or_b64 exec, exec, [[XOR_EXEC]]
 ; GCN-NEXT: [[FINAL_BB]]:
 ; GCN-NEXT: .Lfunc_end0
 define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([9 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <8 x i32>] addrspace(2)* byval %arg2, i32 addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, i32 %arg18, i32 %arg19, float %arg20, i32 %arg21) #0 {
Index: llvm/trunk/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll
@@ -0,0 +1,40 @@
+; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=OPT %s
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+
+; OPT-LABEL: @annotate_unreachable(
+; OPT: call { i1, i64 } @llvm.amdgcn.if(
+; OPT-NOT: call void @llvm.amdgcn.end.cf(
+
+
+; GCN-LABEL: {{^}}annotate_unreachable:
+; GCN: s_and_saveexec_b64
+; GCN-NOT: s_endpgm
+; GCN: .Lfunc_end0
+define void @annotate_unreachable(<4 x float> addrspace(1)* noalias nocapture readonly %arg) #0 {
+bb:
+  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
+  br label %bb1
+
+bb1:                                              ; preds = %bb
+  %tmp2 = sext i32 %tmp to i64
+  %tmp3 = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %arg, i64 %tmp2
+  %tmp4 = load <4 x float>, <4 x float> addrspace(1)* %tmp3, align 16
+  br i1 undef, label %bb3, label %bb5  ; label order reversed
+
+bb3:                                              ; preds = %bb1
+  %tmp6 = extractelement <4 x float> %tmp4, i32 2
+  %tmp7 = fcmp olt float %tmp6, 0.000000e+00
+  br i1 %tmp7, label %bb4, label %bb5
+
+bb4:                                              ; preds = %bb3
+  unreachable
+
+bb5:                                              ; preds = %bb3, %bb1
+  unreachable
+}
+
+declare i32 @llvm.amdgcn.workitem.id.x() #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
Index: llvm/trunk/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
@@ -372,8 +372,9 @@
   }
 
   Value *Exec = popSaved();
-  if (!isa<UndefValue>(Exec))
-    CallInst::Create(EndCf, Exec, "", &*BB->getFirstInsertionPt());
+  Instruction *FirstInsertionPt = &*BB->getFirstInsertionPt();
+  if (!isa<UndefValue>(Exec) && !isa<UnreachableInst>(FirstInsertionPt))
+    CallInst::Create(EndCf, Exec, "", FirstInsertionPt);
 }
 
 /// \brief Annotate the control flow with intrinsics so the backend can


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