[PATCH] D30469: [PowerPC] Expand compare instructions to equivalent GPR code sequences.

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added a comment.

In https://reviews.llvm.org/D30469#692017, @jtony wrote:

> In https://reviews.llvm.org/D30469#691316, @inouehrs wrote:
>
> > Comparison is often used with bit operators, like an example below.
> >  In this example, as long as I test, the transformation is applied only when POS is 0; cmpd + isel are used for cases with POS > 0.
> >  I feel it is nice if we can support comparisons used with bit operators.
> >
> >   const int POS = 1;
> >   long set_flag(long a, long b, long flags) {
> >   	flags |= ((a == b) << POS);
> >   	return flags;
> >   }
> >
>
>
> Hi Hiroshi, that happens because current the SETEQ is implemented in the PPCInstrInfo.td file, which is downstream of DAG2DAG slection, I checked the debug info for the test case you provided here. The zero_extend(setcc) pattern is got converted to select_cc before it has a chance to use the pattern that I added in td file. One possible solution is do that in the DAG2DAG stage like all the other patterns in the CWG, this is a similar issue Nemanja and I have encountered for these pattern in D.2 of CWG.  And there is also a new commit from trunk changes the conversion behavior from setcc to select_cc.  I haven't tried what is the influence of that commit so  I am not sure whether we should move this implementation here to the PPCISelDAG2DAG.cpp file or not.  I will let Kit and Nemanja decide.


This will be handled in a subsequent patch.


https://reviews.llvm.org/D30469