[PATCH] D30549: [X86][SSE] Lower 128-bit vectors to SIGN/ZERO_EXTEND_VECTOR_IN_REG ops.

[Craig Topper via Phabricator via llvm-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM with that one comment.



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Comment at: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2449
   }
   case ISD::SIGN_EXTEND: {
     EVT InVT = Op.getOperand(0).getValueType();
----------------
RKSimon wrote:
> craig.topper wrote:
> > Why no handling for ISD::SIGN_EXTEND_VECTOR_INREG?
> We have no current test coverage that requires this - I'd prefer to add it as a followup if possible.
I'm fine with doing it later. Thanks for adding the TODO.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:17715
                       X86ISD::VSEXT : X86ISD::VZEXT;
-  if (Subtarget.hasSSE41())
+  if (Subtarget.hasSSE41()) {
+    assert(VT.getSizeInBits() > 128 && "Unexpected 128-bit vector extension");
----------------
Maybe clarify the comments here that 128-bits can't get here with SSE41. It's otherwise a bit surprising to see an SSE41 check with an assert requiring larger than 128-bit vectors.


Repository:
  rL LLVM

https://reviews.llvm.org/D30549