[PATCH] D30579: [mips][msa] Fix generation of bmn?zi and bins[lr]i instructions

[Stefan Maksimovic via Phabricator via llvm-commits]

smaksimovic created this revision.

[mips][msa] Fix generation of bmn?zi and  bins[lr]i instructions

We have two cases here, the first one being the following instruction selection from the builtin function:
bmn?zi builtin -> vselect node -> bins[lr]i machine instruction

In case of bmn?zi having an immediate which has either its high or low bits set, a bins[lr] instruction can be selected through the selectVSplatMask[LR] function.
The function counts the number of bits set, and that value is being passed to the bins[lr]i instruction as its immediate, which in turn copies immediate modulo
the size of the element in bits plus 1 as per specs, where we get the off-by-one-error.

The other case is:
bins[lr]i -> vselect node -> bsel.v

If I am not mistaken, the above selection is performed when the mask for the vselect node, which gets generated from the bins[lr]i builtin can't fit into 10 bits
signed, and thus a BUILD_VECTOR node can't be created. In this case, a bsel.v instruction gets selected with a mask having one bit less set than required.


https://reviews.llvm.org/D30579

Files:
  lib/Target/Mips/MipsSEISelDAGToDAG.cpp
  lib/Target/Mips/MipsSEISelLowering.cpp
  test/CodeGen/Mips/msa/bitwise.ll
  test/CodeGen/Mips/msa/bmzi_bmnzi.ll
  test/CodeGen/Mips/msa/i5-b.ll
  test/CodeGen/Mips/msa/immediates.ll

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