[llvm] r296871 - Use APInt::getOneBitSet instead of APInt::getBitsSet for sign bit mask creation

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Fri Mar  3 08:25:46 2017
New Revision: 296871

URL: http://llvm.org/viewvc/llvm-project?rev=296871&view=rev
Log:
Use APInt::getOneBitSet instead of APInt::getBitsSet for sign bit mask creation

Avoids all the unnecessary extra bitrange creation/shift stages.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=296871&r1=296870&r2=296871&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Mar  3 08:25:46 2017
@@ -7702,7 +7702,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_IN
   }
 
   // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
-  if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
+  if (DAG.MaskedValueIsZero(N0, APInt::getOneBitSet(VTBits, EVTBits - 1)))
     return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT.getScalarType());
 
   // fold operands of sext_in_reg based on knowledge that the top bits are not