[PATCH] D30549: [X86][SSE] Lower 128-bit vectors to SIGN/ZERO_EXTEND_VECTOR_IN_REG ops.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.

As described on PR31712, we miss a variety of legalization combines because we lower these to X86ISD::VSEXT/VZEXT despite them having the same functionality. This patch makes 128-bit (SSE41) SIGN/ZERO_EXTEND_VECTOR_IN_REG ops legal, adds the necessary tablegen plumbing and uses a helper 'getExtendInVec' to decide when to use SIGN/ZERO_EXTEND_VECTOR_IN_REG or VSEXT/VZEXT.

We're missing a couple of shuffle combines that will be added in a future patch for review.

Later patches can then support the AVX2 cases as a mixture of SIGN/ZERO_EXTEND and SIGN/ZERO_EXTEND_VECTOR_IN_REG, and then finally deal with the AVX512 cases.


Repository:
  rL LLVM

https://reviews.llvm.org/D30549

Files:
  include/llvm/Target/TargetSelectionDAG.td
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86InstrAVX512.td
  lib/Target/X86/X86InstrSSE.td
  test/CodeGen/X86/2011-10-19-widen_vselect.ll
  test/CodeGen/X86/2011-10-21-widen-cmp.ll
  test/CodeGen/X86/combine-shl.ll
  test/CodeGen/X86/known-bits-vector.ll
  test/CodeGen/X86/pmul.ll
  test/CodeGen/X86/vec_cast2.ll
  test/CodeGen/X86/vec_int_to_fp.ll
  test/CodeGen/X86/vector-zext.ll

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