[llvm] r296777 - [Hexagon] Skip blocks that define vector predicate registers in early-if

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Thu Mar  2 12:10:59 2017
New Revision: 296777

URL: http://llvm.org/viewvc/llvm-project?rev=296777&view=rev
Log:
[Hexagon] Skip blocks that define vector predicate registers in early-if

Added:
    llvm/trunk/test/CodeGen/Hexagon/early-if-vecpred.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp?rev=296777&r1=296776&r2=296777&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp Thu Mar  2 12:10:59 2017
@@ -383,8 +383,14 @@ bool HexagonEarlyIfConversion::isValidCa
       unsigned R = MO.getReg();
       if (!TargetRegisterInfo::isVirtualRegister(R))
         continue;
-      if (MRI->getRegClass(R) != &Hexagon::PredRegsRegClass)
-        continue;
+      switch (MRI->getRegClass(R)->getID()) {
+        case Hexagon::PredRegsRegClassID:
+        case Hexagon::VecPredRegsRegClassID:
+        case Hexagon::VecPredRegs128BRegClassID:
+          break;
+        default:
+          continue;
+      }
       for (auto U = MRI->use_begin(R); U != MRI->use_end(); ++U)
         if (U->getParent()->isPHI())
           return false;

Added: llvm/trunk/test/CodeGen/Hexagon/early-if-vecpred.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/early-if-vecpred.ll?rev=296777&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/early-if-vecpred.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/early-if-vecpred.ll Thu Mar  2 12:10:59 2017
@@ -0,0 +1,37 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; REQUIRES: asserts
+
+; Hexagon early if-conversion used to crash on this testcase due to not
+; recognizing vector predicate registers.
+
+target triple = "hexagon"
+
+; Check that the early if-conversion has not happened.
+
+; CHECK-LABEL: fred
+; CHECK: q{{[0-3]}} = not
+; CHECK: LBB
+; CHECK: if (q{{[0-3]}}) vmem
+define void @fred(i32 %a0) #0 {
+b1:
+  %v2 = tail call <1024 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32 %a0) #2
+  br i1 undef, label %b3, label %b5
+
+b3:                                               ; preds = %b1
+  %v4 = tail call <1024 x i1> @llvm.hexagon.V6.pred.not.128B(<1024 x i1> %v2) #2
+  br label %b5
+
+b5:                                               ; preds = %b3, %b1
+  %v6 = phi <1024 x i1> [ %v4, %b3 ], [ %v2, %b1 ]
+  %v7 = bitcast <1024 x i1> %v6 to <32 x i32>
+  tail call void asm sideeffect "if ($0) vmem($1) = $2;", "q,r,v,~{memory}"(<32 x i32> %v7, <32 x i32>* undef, <32 x i32> undef) #2
+  ret void
+}
+
+declare <1024 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32) #1
+declare <1024 x i1> @llvm.hexagon.V6.pred.not.128B(<1024 x i1>) #1
+
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
+attributes #1 = { nounwind readnone }
+attributes #2 = { nounwind }
+