[PATCH] D30451: [X86][AVX512] Adding new LLVM TableGen backend which generates the EVEX2VEX compressing tables.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: utils/TableGen/X86EVEX2VEXTablesEmitter.cpp:81
+    // Instruction's name starts with one of the entries in the exception list
+    for (const std::string InstStr : ExceptionList) {
+      if (Inst->TheDef->getName().startswith(InstStr))
----------------
Make InstrStr a const std::string&   right now there's a copy there.


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Comment at: utils/TableGen/X86EVEX2VEXTablesEmitter.cpp:111
+
+      {"VPERMILPDZ128mi",     "VPERMILPDmi",     true},
+      {"VPERMILPDZ128ri",     "VPERMILPDri",     true},
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What special about VPERMILPD that need to be manually added?

Same question for the BROADCASTs.


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Comment at: utils/TableGen/X86EVEX2VEXTablesEmitter.cpp:316
+    // (instructions with the same opcode) using function object IsMatch.
+    auto Match = llvm::find_if(VEXInsts[Opcode], IsMatch(EVEXInst));
+    if (Match != VEXInsts[Opcode].end()) {
----------------
How does this handle the MAX and MAXC instructions both having the same opcode information?


https://reviews.llvm.org/D30451