[PATCH] D30539: [tablegen][globalisel] Add support for nested instruction matching.

[Daniel Sanders via Phabricator via llvm-commits]

dsanders created this revision.
Herald added subscribers: kristof.beyls, dberris.
Herald added a reviewer: javed.absar.

Lift the restrictions that prevented the tree walking introduced in the
previous change and add support for patterns like:

  (G_ADD (G_MUL (G_SEXT $src1), (G_SEXT $src2)), $src3) -> SMADDWrrr $dst, $src1, $src2, $src3

Also adds support for G_SEXT and G_ZEXT to support these cases.

One particular aspect of this that I should draw attention to is that I've
tried to be overly conservative in determining the safety of matches that
involve non-adjacent instructions and multiple basic blocks. This is intended
to be used as a cheap initial check and we may add a more expensive check in
the future. The current rules are:

- Reject if any instruction may load/store (we'd need to check for intervening memory operations.
- Reject if any instruction has implicit operands.
- Reject if any instruction has unmodelled side-effects.

See isObviouslySafeToFold().

Another important detail is that (aside from the root of the match) dead
instructions are not yet deleted by the instruction selector. I'll be looking
into this next.


https://reviews.llvm.org/D30539

Files:
  include/llvm/CodeGen/GlobalISel/InstructionSelector.h
  include/llvm/Target/GlobalISel/SelectionDAGCompat.td
  lib/CodeGen/GlobalISel/InstructionSelector.cpp
  lib/Target/AArch64/AArch64InstructionSelector.cpp
  test/CodeGen/AArch64/GlobalISel/arm64-instructionselect-muladd.mir
  test/CodeGen/AArch64/GlobalISel/arm64-instructionselect-sext.mir
  test/CodeGen/AArch64/GlobalISel/arm64-instructionselect-zext.mir
  utils/TableGen/GlobalISelEmitter.cpp

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