[PATCH] D30451: [X86][AVX512] Adding new LLVM TableGen backend which generates the EVEX2VEX compressing tables.

[Ayman Musa via Phabricator via llvm-commits]

aymanmus marked 7 inline comments as done.
aymanmus added inline comments.


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Comment at: utils/TableGen/X86EVEX2VEXTablesEmitter.cpp:68
+  const vector<string> ExceptionList = {
+      "VCVTQQ2PD",
+      "VCVTQQ2PS",
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craig.topper wrote:
> aymanmus wrote:
> > craig.topper wrote:
> > > Why is this a vector and not just a static table of strings?
> > > 
> > > Can you add a comment indicating what each of these corresponds to in VEX just so if someone is curious they easily find it?
> > Any table defined inside the class would require stating the size when defined (ExceptionList[11]), So I figured it's more maintainable this way.
> > The mappings of these instructions to VEX instructions make no sense, there is no "meaning" to the relation.
> Well from a quick look it seemed like some of them were just Q versions of similar instructions in VEX that have WIG right? Is there not some way we can detect that these have W==1 and infer that we shouldn't use a VEX WIG instruction?
If an instruction has WIG value, we map it to either W == 1 or W == 0 or both if they are available.
There is no way to distinguish these specific cases apart from the rest, except for holding an exception list in some way.


https://reviews.llvm.org/D30451