[llvm] r296711 - [DAGCombiner] mulhi + 1 never overflow.

[Amaury Sechet via llvm-commits]

Author: deadalnix
Date: Wed Mar  1 17:44:17 2017
New Revision: 296711

URL: http://llvm.org/viewvc/llvm-project?rev=296711&view=rev
Log:
[DAGCombiner] mulhi + 1 never overflow.

Summary:
This can be used to optimize large multiplications after legalization.

Depends on D29565

Reviewers: mkuper, spatel, RKSimon, zvi, bkramer, aaboud, craig.topper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D29587

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/test/CodeGen/X86/overflow.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=296711&r1=296710&r2=296711&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Mar  1 17:44:17 2017
@@ -2775,6 +2775,19 @@ SelectionDAG::OverflowKind SelectionDAG:
       return OFK_Never;
   }
 
+  // mulhi + 1 never overflow
+  if (N0.getOpcode() == ISD::UMUL_LOHI && N0.getResNo() == 1 &&
+      (~N1Zero & 0x01) == ~N1Zero)
+    return OFK_Never;
+
+  if (N1.getOpcode() == ISD::UMUL_LOHI && N1.getResNo() == 1) {
+    APInt N0Zero, N0One;
+    computeKnownBits(N0, N0Zero, N0One);
+
+    if ((~N0Zero & 0x01) == ~N0Zero)
+      return OFK_Never;
+  }
+
   return OFK_Sometime;
 }
 

Modified: llvm/trunk/test/CodeGen/X86/overflow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/overflow.ll?rev=296711&r1=296710&r2=296711&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/overflow.ll (original)
+++ llvm/trunk/test/CodeGen/X86/overflow.ll Wed Mar  1 17:44:17 2017
@@ -50,10 +50,8 @@ define i128 @mulhioverflow(i64 %a, i64 %
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    mulq %rsi
 ; X64-NEXT:    andl $1, %ecx
-; X64-NEXT:    addq %rdx, %rcx
-; X64-NEXT:    sbbq %rdx, %rdx
-; X64-NEXT:    andl $1, %edx
-; X64-NEXT:    movq %rcx, %rax
+; X64-NEXT:    leaq (%rcx,%rdx), %rax
+; X64-NEXT:    xorl %edx, %edx
 ; X64-NEXT:    retq
   %1 = zext i64 %a to i128
   %2 = zext i64 %b to i128