[PATCH] D30400: For Thumb1, lower ADDC/ADDE/SUBC/SUBE via the glueless ARMISD nodes, same as already done for ARM and Thumb2.
A. Skrobov via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 28 13:49:01 PST 2017
tyomitch added a comment.
> Are you sure we can't use the same codepath we currently use for Thumb2/ARM here?
I don't think we can.
The existing codepath is itself quite hairy: quoting a comment in `ARMInstrInfo.td`,
// Currently, ADDS/SUBS are pseudo opcodes that exist only in the
// selection DAG. They are "lowered" to real ADD/SUB opcodes by
// AdjustInstrPostInstrSelection where we determine whether or not to
// set the "s" bit based on CPSR liveness.
//
// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
// support for an optional CPSR definition that corresponds to the DAG
// node's second value. We can then eliminate the implicit def of CPSR.
For the Thumb1 instructions, we cannot choose "whether or not to set the "s" bit"; it's implicitly set iff the instruction isn't predicated.
https://reviews.llvm.org/D30400
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