[PATCH] D30439: [AMDGPU] New method to estimate register pressure

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: lib/Target/AMDGPU/GCNSchedStrategy.cpp:396
+  const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo*>(TRI);
+  SlotIndex SI = LIS->getInstructionIndex(*begin());
+  assert (SI.isValid());
----------------
vpykhtin wrote:
> Should this specify slot type explicitly? Something like LIS->getInstructionIndex(*begin()).getBaseIndex() ? I just don't know which slot will be returned by default. For example if it return dead slot you will get ranges that actually live after the instruction.
It actually returns first MI in a bundle if any:

```
Mi2IndexMap::const_iterator itr = mi2iMap.find(getBundleStart(MI));

```
I guess that is what I'm looking here for.


Repository:
  rL LLVM

https://reviews.llvm.org/D30439