[llvm] r296455 - [ARM] GlobalISel: Add reg bank mapping for G_GEP

[Diana Picus via llvm-commits]

Author: rovka
Date: Tue Feb 28 03:35:10 2017
New Revision: 296455

URL: http://llvm.org/viewvc/llvm-project?rev=296455&view=rev
Log:
[ARM] GlobalISel: Add reg bank mapping for G_GEP

This should be the same as the mapping for G_ADD etc.

Modified:
    llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
    llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=296455&r1=296454&r2=296455&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Tue Feb 28 03:35:10 2017
@@ -220,6 +220,7 @@ ARMRegisterBankInfo::getInstrMapping(con
   case G_ADD:
   case G_SEXT:
   case G_ZEXT:
+  case G_GEP:
     // FIXME: We're abusing the fact that everything lives in a GPR for now; in
     // the real world we would use different mappings.
     OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];

Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=296455&r1=296454&r2=296455&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Tue Feb 28 03:35:10 2017
@@ -8,6 +8,8 @@
   define void @test_loads() #0 { ret void }
   define void @test_stores() #0 { ret void }
 
+  define void @test_gep() { ret void }
+
   define void @test_fadd_s32() #0 { ret void }
   define void @test_fadd_s64() #0 { ret void }
 
@@ -198,6 +200,31 @@ body:             |
 
 ...
 ---
+name:            test_gep
+# CHECK-LABEL: name: test_gep
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb }
+# CHECK: - { id: 1, class: gprb }
+# CHECK: - { id: 2, class: gprb }
+
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0, %r1
+
+    %0(p0) = COPY %r0
+    %1(s32) = COPY %r1
+    %2(p0) = G_GEP %0, %1(s32)
+    %r0 = COPY %2(p0)
+    BX_RET 14, _, implicit %r0
+...
+---
 name:            test_fadd_s32
 # CHECK-LABEL: name: test_fadd_s32
 legalized:       true