[PATCH] D30379: [SelectionDAG] Make SelectionDAG aware of the known bits in UADDO and SADDO.
Amaury SECHET via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 26 17:30:55 PST 2017
deadalnix updated this revision to Diff 89824.
deadalnix added a comment.
Fix the ISD::SUB case, which needs to was threated as ADDE. It is probably possible to do somethign better, but it's good enough for now.
https://reviews.llvm.org/D30379
Files:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
test/CodeGen/X86/known-bits.ll
Index: test/CodeGen/X86/known-bits.ll
===================================================================
--- test/CodeGen/X86/known-bits.ll
+++ test/CodeGen/X86/known-bits.ll
@@ -197,10 +197,10 @@
; X64-NEXT: shlq $32, %rdi
; X64-NEXT: shlq $32, %rsi
; X64-NEXT: addq %rdi, %rsi
-; X64-NEXT: setb %cl
+; X64-NEXT: setb %al
; X64-NEXT: seto %dl
-; X64-NEXT: leal (%rsi,%rsi), %eax
-; X64-NEXT: orb %cl, %dl
+; X64-NEXT: orb %al, %dl
+; X64-NEXT: xorl %eax, %eax
; X64-NEXT: retq
%1 = shl i64 %a0, 32
%2 = shl i64 %a1, 32
Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2297,8 +2297,6 @@
KnownOne &= KnownOne2;
KnownZero &= KnownZero2;
break;
- case ISD::SADDO:
- case ISD::UADDO:
case ISD::SSUBO:
case ISD::USUBO:
case ISD::SMULO:
@@ -2505,6 +2503,17 @@
}
LLVM_FALLTHROUGH;
}
+ case ISD::UADDO:
+ case ISD::SADDO:
+ if (Op.getResNo() == 1) {
+ // If we know the result of a setcc has the top bits zero, use this info.
+ if (TLI->getBooleanContents(Op.getOperand(0).getValueType()) ==
+ TargetLowering::ZeroOrOneBooleanContent &&
+ BitWidth > 1)
+ KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
+ break;
+ }
+ LLVM_FALLTHROUGH;
case ISD::ADD:
case ISD::ADDC:
case ISD::ADDE: {
@@ -2527,19 +2536,19 @@
KnownZeroLow = std::min(KnownZeroLow,
KnownZero2.countTrailingOnes());
- if (Opcode == ISD::ADD || Opcode == ISD::ADDC) {
- KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroLow);
- if (KnownZeroHigh > 1)
- KnownZero |= APInt::getHighBitsSet(BitWidth, KnownZeroHigh - 1);
+ if (Opcode == ISD::ADDE || Opcode == ISD::SUB) {
+ // With ADDE, a carry bit may be added in, so we can only use this
+ // information if we know (at least) that the low two bits are clear.
+ // We then return to the caller that the low bit is unknown but that
+ // other bits are known zero.
+ if (KnownZeroLow >= 2)
+ KnownZero |= APInt::getBitsSet(BitWidth, 1, KnownZeroLow);
break;
}
- // With ADDE, a carry bit may be added in, so we can only use this
- // information if we know (at least) that the low two bits are clear. We
- // then return to the caller that the low bit is unknown but that other bits
- // are known zero.
- if (KnownZeroLow >= 2) // ADDE
- KnownZero |= APInt::getBitsSet(BitWidth, 1, KnownZeroLow);
+ KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroLow);
+ if (KnownZeroHigh > 1)
+ KnownZero |= APInt::getHighBitsSet(BitWidth, KnownZeroHigh - 1);
break;
}
case ISD::SREM:
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