[llvm] r296122 - [ARM] GlobalISel: Select G_STORE
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 24 06:01:28 PST 2017
Author: rovka
Date: Fri Feb 24 08:01:27 2017
New Revision: 296122
URL: http://llvm.org/viewvc/llvm-project?rev=296122&view=rev
Log:
[ARM] GlobalISel: Select G_STORE
Same as selecting G_LOAD.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
Modified: llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp?rev=296122&r1=296121&r2=296122&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp Fri Feb 24 08:01:27 2017
@@ -189,36 +189,39 @@ static unsigned selectSimpleExtOpc(unsig
return Opc;
}
-/// Select the opcode for simple loads. For types smaller than 32 bits, the
-/// value will be zero extended. Returns G_LOAD if it doesn't know how to select
-/// an opcode.
-static unsigned selectLoadOpCode(unsigned RegBank, unsigned Size) {
+/// Select the opcode for simple loads and stores. For types smaller than 32
+/// bits, the value will be zero extended. Returns the original opcode if it
+/// doesn't know how to select a better one.
+static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
+ unsigned Size) {
+ bool isStore = Opc == TargetOpcode::G_STORE;
+
if (RegBank == ARM::GPRRegBankID) {
switch (Size) {
case 1:
case 8:
- return ARM::LDRBi12;
+ return isStore ? ARM::STRBi12 : ARM::LDRBi12;
case 16:
- return ARM::LDRH;
+ return isStore ? ARM::STRH : ARM::LDRH;
case 32:
- return ARM::LDRi12;
+ return isStore ? ARM::STRi12 : ARM::LDRi12;
default:
- return TargetOpcode::G_LOAD;
+ return Opc;
}
}
if (RegBank == ARM::FPRRegBankID) {
switch (Size) {
case 32:
- return ARM::VLDRS;
+ return isStore ? ARM::VSTRS : ARM::VLDRS;
case 64:
- return ARM::VLDRD;
+ return isStore ? ARM::VSTRD : ARM::VLDRD;
default:
- return TargetOpcode::G_LOAD;
+ return Opc;
}
}
- return TargetOpcode::G_LOAD;
+ return Opc;
}
bool ARMInstructionSelector::select(MachineInstr &I) const {
@@ -309,6 +312,7 @@ bool ARMInstructionSelector::select(Mach
I.setDesc(TII.get(ARM::ADDri));
MIB.addImm(0).add(predOps(ARMCC::AL)).add(condCodeOp());
break;
+ case G_STORE:
case G_LOAD: {
const auto &MemOp = **I.memoperands_begin();
if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) {
@@ -323,15 +327,15 @@ bool ARMInstructionSelector::select(Mach
const auto ValSize = ValTy.getSizeInBits();
assert((ValSize != 64 || TII.getSubtarget().hasVFP2()) &&
- "Don't know how to load 64-bit value without VFP");
+ "Don't know how to load/store 64-bit value without VFP");
- const auto NewOpc = selectLoadOpCode(RegBank, ValSize);
- if (NewOpc == G_LOAD)
+ const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize);
+ if (NewOpc == G_LOAD || NewOpc == G_STORE)
return false;
I.setDesc(TII.get(NewOpc));
- if (NewOpc == ARM::LDRH)
+ if (NewOpc == ARM::LDRH || NewOpc == ARM::STRH)
// LDRH has a funny addressing mode (there's already a FIXME for it).
MIB.addReg(0);
MIB.addImm(0).add(predOps(ARMCC::AL));
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=296122&r1=296121&r2=296122&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Fri Feb 24 08:01:27 2017
@@ -16,6 +16,8 @@
define void @test_load_f32() #0 { ret void }
define void @test_load_f64() #0 { ret void }
+ define void @test_stores() #0 { ret void }
+
define void @test_soft_fp_double() #0 { ret void }
attributes #0 = { "target-features"="+vfp2,-neonfp" }
@@ -387,6 +389,54 @@ body: |
; CHECK: BX_RET 14, _, implicit %d0
...
---
+name: test_stores
+# CHECK-LABEL: name: test_stores
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+ - { id: 4, class: fprb }
+ - { id: 5, class: fprb }
+# CHECK: id: [[P:[0-9]+]], class: gpr
+# CHECK: id: [[I8:[0-9]+]], class: gpr
+# CHECK: id: [[I16:[0-9]+]], class: gpr
+# CHECK: id: [[I32:[0-9]+]], class: gpr
+# CHECK: id: [[F32:[0-9]+]], class: spr
+# CHECK: id: [[F64:[0-9]+]], class: dpr
+body: |
+ bb.0:
+ liveins: %r0, %r1, %r2, %r3
+
+ %0(p0) = COPY %r0
+ %1(s8) = COPY %r3
+ %2(s16) = COPY %r2
+ %3(s32) = COPY %r1
+ %4(s32) = COPY %s0
+ %5(s64) = COPY %d2
+
+ G_STORE %1(s8), %0(p0) :: (store 1)
+ ; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, _
+
+ G_STORE %2(s16), %0(p0) :: (store 2)
+ ; CHECK: STRH %[[I16]], %[[P]], _, 0, 14, _
+
+ G_STORE %3(s32), %0(p0) :: (store 4)
+ ; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, _
+
+ G_STORE %4(s32), %0(p0) :: (store 4)
+ ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, _
+
+ G_STORE %5(s64), %0(p0) :: (store 8)
+ ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, _
+
+ BX_RET 14, _
+...
+---
name: test_soft_fp_double
# CHECK-LABEL: name: test_soft_fp_double
legalized: true
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