[PATCH] D29639: [SelectionDAG] Add a signed integer absolute ISD node

[James Greenhalgh via Phabricator via llvm-commits]

jgreenhalgh added a comment.

In https://reviews.llvm.org/D29639#682183, @jmolloy wrote:

> Hi,
>
> Having asked around: The way we define this is that the VABS instruction takes a signed integer and outputs an unsigned integer, getting around this problem.
>
> However, I believe the output of VABS(INT_MIN) is indeed bit-identical to INT_MIN.
>
> + @jgreenhalgh  to confirm I haven't mangled his explanation.


Only a minor tweak on a pedantic point - the instruction doesn't really have an idea of signed/unsigned - just bits. The effect is as if you were calculating in an unsigned value of the same number of bits as the input.

That doesn't hold for the intrinsics which are all signed -> signed. But the behaviour there is ABS(INT_MIN) -> INT_MIN, so the behaviour in this patch looks fine for ARM/AArch64 Advanced SIMD.


Repository:
  rL LLVM

https://reviews.llvm.org/D29639