[llvm] r295789 - AMDGPU: Remove llvm.AMDGPU.clamp intrinsic
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 21 15:46:04 PST 2017
Author: arsenm
Date: Tue Feb 21 17:46:04 2017
New Revision: 295789
URL: http://llvm.org/viewvc/llvm-project?rev=295789&view=rev
Log:
AMDGPU: Remove llvm.AMDGPU.clamp intrinsic
Removed:
llvm/trunk/test/CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUIntrinsics.td
llvm/trunk/test/CodeGen/AMDGPU/big_alu.ll
llvm/trunk/test/CodeGen/AMDGPU/kcache-fold.ll
llvm/trunk/test/CodeGen/AMDGPU/pv.ll
llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll
llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll
llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop.ll
llvm/trunk/test/CodeGen/AMDGPU/si-sgpr-spill.ll
llvm/trunk/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp?rev=295789&r1=295788&r2=295789&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp Tue Feb 21 17:46:04 2017
@@ -1013,17 +1013,6 @@ SDValue AMDGPUTargetLowering::LowerINTRI
switch (IntrinsicID) {
default: return Op;
- case AMDGPUIntrinsic::AMDGPU_clamp: {
- // Deprecated in favor of emitting min/max combo or fmed3.
- ConstantFPSDNode *CSrc1 = dyn_cast<ConstantFPSDNode>(Op.getOperand(2));
- ConstantFPSDNode *CSrc2 = dyn_cast<ConstantFPSDNode>(Op.getOperand(3));
- if (CSrc1 && CSrc2 && CSrc1->isZero() && CSrc2->isExactlyValue(1.0))
- return DAG.getNode(AMDGPUISD::CLAMP, DL, VT, Op.getOperand(1));
-
- SDValue Max = DAG.getNode(ISD::FMAXNUM, DL, VT, Op.getOperand(1),
- Op.getOperand(2));
- return DAG.getNode(ISD::FMINNUM, DL, VT, Max, Op.getOperand(3));
- }
case AMDGPUIntrinsic::AMDGPU_bfe_i32:
return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
Op.getOperand(1),
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUIntrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUIntrinsics.td?rev=295789&r1=295788&r2=295789&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUIntrinsics.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUIntrinsics.td Tue Feb 21 17:46:04 2017
@@ -12,8 +12,6 @@
//===----------------------------------------------------------------------===//
let TargetPrefix = "AMDGPU", isTarget = 1 in {
- def int_AMDGPU_clamp : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
-
def int_AMDGPU_kill : Intrinsic<[], [llvm_float_ty], []>;
def int_AMDGPU_kilp : Intrinsic<[], [], []>;
Modified: llvm/trunk/test/CodeGen/AMDGPU/big_alu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/big_alu.ll?rev=295789&r1=295788&r2=295789&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/big_alu.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/big_alu.ll Tue Feb 21 17:46:04 2017
@@ -2,7 +2,7 @@
; This test ensures that R600 backend can handle ifcvt properly
-define amdgpu_ps void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg %reg8, <4 x float> inreg %reg9) {
+define amdgpu_ps void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg %reg8, <4 x float> inreg %reg9) #0 {
main_body:
%tmp = extractelement <4 x float> %reg0, i32 0
%tmp1 = extractelement <4 x float> %reg0, i32 1
@@ -224,28 +224,31 @@ ENDIF136:
%result.i = fadd float %mul.i, %one.sub.ac.i
%tmp204 = fadd float %result.i, 0x3FF4CCCCC0000000
%tmp205 = fmul float %tmp204, 0x3FE1C71C80000000
- %tmp206 = call float @llvm.AMDGPU.clamp.f32(float %tmp205, float 0.000000e+00, float 1.000000e+00)
+ %max.0.i = call float @llvm.maxnum.f32(float %tmp205, float 0.000000e+00)
+ %clamp.i = call float @llvm.minnum.f32(float %max.0.i, float 1.000000e+00)
%tmp207 = fadd float %result.i, 0x3FF4CCCCC0000000
%tmp208 = fmul float %tmp207, 0x3FE1C71C80000000
- %tmp209 = call float @llvm.AMDGPU.clamp.f32(float %tmp208, float 0.000000e+00, float 1.000000e+00)
+ %max.0.i15 = call float @llvm.maxnum.f32(float %tmp208, float 0.000000e+00)
+ %clamp.i16 = call float @llvm.minnum.f32(float %max.0.i15, float 1.000000e+00)
%tmp210 = fadd float %result.i, 2.000000e+00
%tmp211 = fmul float %tmp210, 0x3FD611A7A0000000
- %tmp212 = call float @llvm.AMDGPU.clamp.f32(float %tmp211, float 0.000000e+00, float 1.000000e+00)
- %tmp213 = fmul float 2.000000e+00, %tmp206
+ %max.0.i13 = call float @llvm.maxnum.f32(float %tmp211, float 0.000000e+00)
+ %clamp.i14 = call float @llvm.minnum.f32(float %max.0.i13, float 1.000000e+00)
+ %tmp213 = fmul float 2.000000e+00, %clamp.i
%tmp214 = fsub float -0.000000e+00, %tmp213
%tmp215 = fadd float 3.000000e+00, %tmp214
- %tmp216 = fmul float %tmp206, %tmp215
- %tmp217 = fmul float %tmp206, %tmp216
- %tmp218 = fmul float 2.000000e+00, %tmp209
+ %tmp216 = fmul float %clamp.i, %tmp215
+ %tmp217 = fmul float %clamp.i, %tmp216
+ %tmp218 = fmul float 2.000000e+00, %clamp.i16
%tmp219 = fsub float -0.000000e+00, %tmp218
%tmp220 = fadd float 3.000000e+00, %tmp219
- %tmp221 = fmul float %tmp209, %tmp220
- %tmp222 = fmul float %tmp209, %tmp221
- %tmp223 = fmul float 2.000000e+00, %tmp212
+ %tmp221 = fmul float %clamp.i16, %tmp220
+ %tmp222 = fmul float %clamp.i16, %tmp221
+ %tmp223 = fmul float 2.000000e+00, %clamp.i14
%tmp224 = fsub float -0.000000e+00, %tmp223
%tmp225 = fadd float 3.000000e+00, %tmp224
- %tmp226 = fmul float %tmp212, %tmp225
- %tmp227 = fmul float %tmp212, %tmp226
+ %tmp226 = fmul float %clamp.i14, %tmp225
+ %tmp227 = fmul float %clamp.i14, %tmp226
%tmp228 = fmul float %tmp26, 0x3F368B5CC0000000
%tmp229 = fmul float %tmp27, 0x3F368B5CC0000000
%tmp230 = insertelement <4 x float> undef, float %tmp228, i32 0
@@ -282,28 +285,31 @@ ENDIF136:
%tmp261 = fmul float %tmp257, 0.000000e+00
%tmp262 = fadd float %result.i, 0x3FF4CCCCC0000000
%tmp263 = fmul float %tmp262, 0x3FE1C71C80000000
- %tmp264 = call float @llvm.AMDGPU.clamp.f32(float %tmp263, float 0.000000e+00, float 1.000000e+00)
+ %max.0.i11 = call float @llvm.maxnum.f32(float %tmp263, float 0.000000e+00)
+ %clamp.i12 = call float @llvm.minnum.f32(float %max.0.i11, float 1.000000e+00)
%tmp265 = fadd float %result.i, 0x3FF4CCCCC0000000
%tmp266 = fmul float %tmp265, 0x3FE1C71C80000000
- %tmp267 = call float @llvm.AMDGPU.clamp.f32(float %tmp266, float 0.000000e+00, float 1.000000e+00)
+ %max.0.i9 = call float @llvm.maxnum.f32(float %tmp266, float 0.000000e+00)
+ %clamp.i10 = call float @llvm.minnum.f32(float %max.0.i9, float 1.000000e+00)
%tmp268 = fadd float %result.i, 2.000000e+00
%tmp269 = fmul float %tmp268, 0x3FD611A7A0000000
- %tmp270 = call float @llvm.AMDGPU.clamp.f32(float %tmp269, float 0.000000e+00, float 1.000000e+00)
- %tmp271 = fmul float 2.000000e+00, %tmp264
+ %max.0.i7 = call float @llvm.maxnum.f32(float %tmp269, float 0.000000e+00)
+ %clamp.i8 = call float @llvm.minnum.f32(float %max.0.i7, float 1.000000e+00)
+ %tmp271 = fmul float 2.000000e+00, %clamp.i12
%tmp272 = fsub float -0.000000e+00, %tmp271
%tmp273 = fadd float 3.000000e+00, %tmp272
- %tmp274 = fmul float %tmp264, %tmp273
- %tmp275 = fmul float %tmp264, %tmp274
- %tmp276 = fmul float 2.000000e+00, %tmp267
+ %tmp274 = fmul float %clamp.i12, %tmp273
+ %tmp275 = fmul float %clamp.i12, %tmp274
+ %tmp276 = fmul float 2.000000e+00, %clamp.i10
%tmp277 = fsub float -0.000000e+00, %tmp276
%tmp278 = fadd float 3.000000e+00, %tmp277
- %tmp279 = fmul float %tmp267, %tmp278
- %tmp280 = fmul float %tmp267, %tmp279
- %tmp281 = fmul float 2.000000e+00, %tmp270
+ %tmp279 = fmul float %clamp.i10, %tmp278
+ %tmp280 = fmul float %clamp.i10, %tmp279
+ %tmp281 = fmul float 2.000000e+00, %clamp.i8
%tmp282 = fsub float -0.000000e+00, %tmp281
%tmp283 = fadd float 3.000000e+00, %tmp282
- %tmp284 = fmul float %tmp270, %tmp283
- %tmp285 = fmul float %tmp270, %tmp284
+ %tmp284 = fmul float %clamp.i8, %tmp283
+ %tmp285 = fmul float %clamp.i8, %tmp284
%tmp286 = fmul float %tmp26, 0x3F22DFD6A0000000
%tmp287 = fmul float %tmp27, 0x3F22DFD6A0000000
%tmp288 = insertelement <4 x float> undef, float %tmp286, i32 0
@@ -390,7 +396,8 @@ ENDIF136:
%tmp369 = fadd float %tmp368, %tmp367
%tmp370 = fadd float %tmp369, 0xBFEFAE1480000000
%tmp371 = fmul float %tmp370, 0xC023FFFFC0000000
- %tmp372 = call float @llvm.AMDGPU.clamp.f32(float %tmp371, float 0.000000e+00, float 1.000000e+00)
+ %max.0.i5 = call float @llvm.maxnum.f32(float %tmp371, float 0.000000e+00)
+ %clamp.i6 = call float @llvm.minnum.f32(float %max.0.i5, float 1.000000e+00)
%tmp373 = fsub float -0.000000e+00, %tmp339
%tmp374 = fadd float %result.i, %tmp373
%tmp375 = fadd float %tmp374, 0x3FBEB851E0000000
@@ -416,12 +423,13 @@ ENDIF136:
%tmp395 = fadd float %tmp394, %tmp393
%tmp396 = fadd float %tmp395, 0xBFEFAE1480000000
%tmp397 = fmul float %tmp396, 0xC0490001A0000000
- %tmp398 = call float @llvm.AMDGPU.clamp.f32(float %tmp397, float 0.000000e+00, float 1.000000e+00)
- %tmp399 = fmul float 2.000000e+00, %tmp372
+ %max.0.i3 = call float @llvm.maxnum.f32(float %tmp397, float 0.000000e+00)
+ %clamp.i4 = call float @llvm.minnum.f32(float %max.0.i3, float 1.000000e+00)
+ %tmp399 = fmul float 2.000000e+00, %clamp.i6
%tmp400 = fsub float -0.000000e+00, %tmp399
%tmp401 = fadd float 3.000000e+00, %tmp400
- %tmp402 = fmul float %tmp372, %tmp401
- %tmp403 = fmul float %tmp372, %tmp402
+ %tmp402 = fmul float %clamp.i6, %tmp401
+ %tmp403 = fmul float %clamp.i6, %tmp402
%one.sub.a.i169 = fsub float 1.000000e+00, %tmp403
%one.sub.ac.i170 = fmul float %one.sub.a.i169, %tmp349
%mul.i171 = fmul float %tmp258, %tmp349
@@ -438,11 +446,11 @@ ENDIF136:
%one.sub.ac.i158 = fmul float %one.sub.a.i157, 0.000000e+00
%mul.i159 = fmul float %tmp261, 0.000000e+00
%result.i160 = fadd float %mul.i159, %one.sub.ac.i158
- %tmp404 = fmul float 2.000000e+00, %tmp398
+ %tmp404 = fmul float 2.000000e+00, %clamp.i4
%tmp405 = fsub float -0.000000e+00, %tmp404
%tmp406 = fadd float 3.000000e+00, %tmp405
- %tmp407 = fmul float %tmp398, %tmp406
- %tmp408 = fmul float %tmp398, %tmp407
+ %tmp407 = fmul float %clamp.i4, %tmp406
+ %tmp408 = fmul float %clamp.i4, %tmp407
%one.sub.a.i153 = fsub float 1.000000e+00, %tmp408
%one.sub.ac.i154 = fmul float %one.sub.a.i153, %tmp375
%mul.i155 = fmul float %tmp258, %tmp375
@@ -1157,12 +1165,13 @@ IF179:
%tmp882 = fadd float %tmp881, %tmp880
%tmp883 = fadd float %tmp882, 0xBFEFAE1480000000
%tmp884 = fmul float %tmp883, 0xC043FFFE20000000
- %tmp885 = call float @llvm.AMDGPU.clamp.f32(float %tmp884, float 0.000000e+00, float 1.000000e+00)
- %tmp886 = fmul float 2.000000e+00, %tmp885
+ %max.0.i1 = call float @llvm.maxnum.f32(float %tmp884, float 0.000000e+00)
+ %clamp.i2 = call float @llvm.minnum.f32(float %max.0.i1, float 1.000000e+00)
+ %tmp886 = fmul float 2.000000e+00, %clamp.i2
%tmp887 = fsub float -0.000000e+00, %tmp886
%tmp888 = fadd float 3.000000e+00, %tmp887
- %tmp889 = fmul float %tmp885, %tmp888
- %tmp890 = fmul float %tmp885, %tmp889
+ %tmp889 = fmul float %clamp.i2, %tmp888
+ %tmp890 = fmul float %clamp.i2, %tmp889
%one.sub.a.i41 = fsub float 1.000000e+00, %tmp890
%one.sub.ac.i42 = fmul float %one.sub.a.i41, %tmp866
%mul.i43 = fmul float %temp84.5, %tmp866
@@ -1288,25 +1297,14 @@ ENDIF178:
ret void
}
-; Function Attrs: nounwind readnone
-declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #0
-
-; Function Attrs: nounwind readnone
-declare float @llvm.r600.recipsqrt.clamped.f32(float) #0
-
-; Function Attrs: nounwind readonly
+declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #1
+declare float @llvm.r600.recipsqrt.clamped.f32(float) #1
declare float @llvm.fabs.f32(float) #1
-
-; Function Attrs: nounwind readnone
-declare float @llvm.exp2.f32(float) #0
-
-; Function Attrs: nounwind readnone
-declare float @llvm.AMDGPU.clamp.f32(float, float, float) #0
-
+declare float @llvm.exp2.f32(float) #1
declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
+declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) #1
+declare float @llvm.minnum.f32(float, float) #1
+declare float @llvm.maxnum.f32(float, float) #1
-; Function Attrs: nounwind readnone
-declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) #0
-
-attributes #0 = { nounwind readnone }
-attributes #1 = { nounwind readonly }
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
Modified: llvm/trunk/test/CodeGen/AMDGPU/kcache-fold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/kcache-fold.ll?rev=295789&r1=295788&r2=295789&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/kcache-fold.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/kcache-fold.ll Tue Feb 21 17:46:04 2017
@@ -1,100 +1,112 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s
; CHECK: {{^}}main1:
; CHECK: MOV * T{{[0-9]+\.[XYZW], KC0}}
-define void @main1() {
+define void @main1() #0 {
main_body:
- %0 = load <4 x float>, <4 x float> addrspace(8)* null
- %1 = extractelement <4 x float> %0, i32 0
- %2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %3 = extractelement <4 x float> %2, i32 0
- %4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %5 = extractelement <4 x float> %4, i32 0
- %6 = fcmp ogt float %1, 0.000000e+00
- %7 = select i1 %6, float %3, float %5
- %8 = load <4 x float>, <4 x float> addrspace(8)* null
- %9 = extractelement <4 x float> %8, i32 1
- %10 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %11 = extractelement <4 x float> %10, i32 1
- %12 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %13 = extractelement <4 x float> %12, i32 1
- %14 = fcmp ogt float %9, 0.000000e+00
- %15 = select i1 %14, float %11, float %13
- %16 = load <4 x float>, <4 x float> addrspace(8)* null
- %17 = extractelement <4 x float> %16, i32 2
- %18 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %19 = extractelement <4 x float> %18, i32 2
- %20 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %21 = extractelement <4 x float> %20, i32 2
- %22 = fcmp ogt float %17, 0.000000e+00
- %23 = select i1 %22, float %19, float %21
- %24 = load <4 x float>, <4 x float> addrspace(8)* null
- %25 = extractelement <4 x float> %24, i32 3
- %26 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %27 = extractelement <4 x float> %26, i32 3
- %28 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %29 = extractelement <4 x float> %28, i32 3
- %30 = fcmp ogt float %25, 0.000000e+00
- %31 = select i1 %30, float %27, float %29
- %32 = call float @llvm.AMDGPU.clamp.f32(float %7, float 0.000000e+00, float 1.000000e+00)
- %33 = call float @llvm.AMDGPU.clamp.f32(float %15, float 0.000000e+00, float 1.000000e+00)
- %34 = call float @llvm.AMDGPU.clamp.f32(float %23, float 0.000000e+00, float 1.000000e+00)
- %35 = call float @llvm.AMDGPU.clamp.f32(float %31, float 0.000000e+00, float 1.000000e+00)
- %36 = insertelement <4 x float> undef, float %32, i32 0
- %37 = insertelement <4 x float> %36, float %33, i32 1
- %38 = insertelement <4 x float> %37, float %34, i32 2
- %39 = insertelement <4 x float> %38, float %35, i32 3
- call void @llvm.r600.store.swizzle(<4 x float> %39, i32 0, i32 0)
+ %tmp = load <4 x float>, <4 x float> addrspace(8)* null
+ %tmp7 = extractelement <4 x float> %tmp, i32 0
+ %tmp8 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+ %tmp9 = extractelement <4 x float> %tmp8, i32 0
+ %tmp10 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+ %tmp11 = extractelement <4 x float> %tmp10, i32 0
+ %tmp12 = fcmp ogt float %tmp7, 0.000000e+00
+ %tmp13 = select i1 %tmp12, float %tmp9, float %tmp11
+ %tmp14 = load <4 x float>, <4 x float> addrspace(8)* null
+ %tmp15 = extractelement <4 x float> %tmp14, i32 1
+ %tmp16 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+ %tmp17 = extractelement <4 x float> %tmp16, i32 1
+ %tmp18 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+ %tmp19 = extractelement <4 x float> %tmp18, i32 1
+ %tmp20 = fcmp ogt float %tmp15, 0.000000e+00
+ %tmp21 = select i1 %tmp20, float %tmp17, float %tmp19
+ %tmp22 = load <4 x float>, <4 x float> addrspace(8)* null
+ %tmp23 = extractelement <4 x float> %tmp22, i32 2
+ %tmp24 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+ %tmp25 = extractelement <4 x float> %tmp24, i32 2
+ %tmp26 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+ %tmp27 = extractelement <4 x float> %tmp26, i32 2
+ %tmp28 = fcmp ogt float %tmp23, 0.000000e+00
+ %tmp29 = select i1 %tmp28, float %tmp25, float %tmp27
+ %tmp30 = load <4 x float>, <4 x float> addrspace(8)* null
+ %tmp31 = extractelement <4 x float> %tmp30, i32 3
+ %tmp32 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+ %tmp33 = extractelement <4 x float> %tmp32, i32 3
+ %tmp34 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+ %tmp35 = extractelement <4 x float> %tmp34, i32 3
+ %tmp36 = fcmp ogt float %tmp31, 0.000000e+00
+ %tmp37 = select i1 %tmp36, float %tmp33, float %tmp35
+ %max.0.i = call float @llvm.maxnum.f32(float %tmp13, float 0.000000e+00)
+ %clamp.i = call float @llvm.minnum.f32(float %max.0.i, float 1.000000e+00)
+ %max.0.i5 = call float @llvm.maxnum.f32(float %tmp21, float 0.000000e+00)
+ %clamp.i6 = call float @llvm.minnum.f32(float %max.0.i5, float 1.000000e+00)
+ %max.0.i3 = call float @llvm.maxnum.f32(float %tmp29, float 0.000000e+00)
+ %clamp.i4 = call float @llvm.minnum.f32(float %max.0.i3, float 1.000000e+00)
+ %max.0.i1 = call float @llvm.maxnum.f32(float %tmp37, float 0.000000e+00)
+ %clamp.i2 = call float @llvm.minnum.f32(float %max.0.i1, float 1.000000e+00)
+ %tmp38 = insertelement <4 x float> undef, float %clamp.i, i32 0
+ %tmp39 = insertelement <4 x float> %tmp38, float %clamp.i6, i32 1
+ %tmp40 = insertelement <4 x float> %tmp39, float %clamp.i4, i32 2
+ %tmp41 = insertelement <4 x float> %tmp40, float %clamp.i2, i32 3
+ call void @llvm.r600.store.swizzle(<4 x float> %tmp41, i32 0, i32 0)
ret void
}
; CHECK: {{^}}main2:
; CHECK-NOT: MOV
-define void @main2() {
+define void @main2() #0 {
main_body:
- %0 = load <4 x float>, <4 x float> addrspace(8)* null
- %1 = extractelement <4 x float> %0, i32 0
- %2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %3 = extractelement <4 x float> %2, i32 0
- %4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %5 = extractelement <4 x float> %4, i32 1
- %6 = fcmp ogt float %1, 0.000000e+00
- %7 = select i1 %6, float %3, float %5
- %8 = load <4 x float>, <4 x float> addrspace(8)* null
- %9 = extractelement <4 x float> %8, i32 1
- %10 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %11 = extractelement <4 x float> %10, i32 0
- %12 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %13 = extractelement <4 x float> %12, i32 1
- %14 = fcmp ogt float %9, 0.000000e+00
- %15 = select i1 %14, float %11, float %13
- %16 = load <4 x float>, <4 x float> addrspace(8)* null
- %17 = extractelement <4 x float> %16, i32 2
- %18 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %19 = extractelement <4 x float> %18, i32 3
- %20 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %21 = extractelement <4 x float> %20, i32 2
- %22 = fcmp ogt float %17, 0.000000e+00
- %23 = select i1 %22, float %19, float %21
- %24 = load <4 x float>, <4 x float> addrspace(8)* null
- %25 = extractelement <4 x float> %24, i32 3
- %26 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %27 = extractelement <4 x float> %26, i32 3
- %28 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %29 = extractelement <4 x float> %28, i32 2
- %30 = fcmp ogt float %25, 0.000000e+00
- %31 = select i1 %30, float %27, float %29
- %32 = call float @llvm.AMDGPU.clamp.f32(float %7, float 0.000000e+00, float 1.000000e+00)
- %33 = call float @llvm.AMDGPU.clamp.f32(float %15, float 0.000000e+00, float 1.000000e+00)
- %34 = call float @llvm.AMDGPU.clamp.f32(float %23, float 0.000000e+00, float 1.000000e+00)
- %35 = call float @llvm.AMDGPU.clamp.f32(float %31, float 0.000000e+00, float 1.000000e+00)
- %36 = insertelement <4 x float> undef, float %32, i32 0
- %37 = insertelement <4 x float> %36, float %33, i32 1
- %38 = insertelement <4 x float> %37, float %34, i32 2
- %39 = insertelement <4 x float> %38, float %35, i32 3
- call void @llvm.r600.store.swizzle(<4 x float> %39, i32 0, i32 0)
+ %tmp = load <4 x float>, <4 x float> addrspace(8)* null
+ %tmp7 = extractelement <4 x float> %tmp, i32 0
+ %tmp8 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+ %tmp9 = extractelement <4 x float> %tmp8, i32 0
+ %tmp10 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+ %tmp11 = extractelement <4 x float> %tmp10, i32 1
+ %tmp12 = fcmp ogt float %tmp7, 0.000000e+00
+ %tmp13 = select i1 %tmp12, float %tmp9, float %tmp11
+ %tmp14 = load <4 x float>, <4 x float> addrspace(8)* null
+ %tmp15 = extractelement <4 x float> %tmp14, i32 1
+ %tmp16 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+ %tmp17 = extractelement <4 x float> %tmp16, i32 0
+ %tmp18 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+ %tmp19 = extractelement <4 x float> %tmp18, i32 1
+ %tmp20 = fcmp ogt float %tmp15, 0.000000e+00
+ %tmp21 = select i1 %tmp20, float %tmp17, float %tmp19
+ %tmp22 = load <4 x float>, <4 x float> addrspace(8)* null
+ %tmp23 = extractelement <4 x float> %tmp22, i32 2
+ %tmp24 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+ %tmp25 = extractelement <4 x float> %tmp24, i32 3
+ %tmp26 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+ %tmp27 = extractelement <4 x float> %tmp26, i32 2
+ %tmp28 = fcmp ogt float %tmp23, 0.000000e+00
+ %tmp29 = select i1 %tmp28, float %tmp25, float %tmp27
+ %tmp30 = load <4 x float>, <4 x float> addrspace(8)* null
+ %tmp31 = extractelement <4 x float> %tmp30, i32 3
+ %tmp32 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+ %tmp33 = extractelement <4 x float> %tmp32, i32 3
+ %tmp34 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+ %tmp35 = extractelement <4 x float> %tmp34, i32 2
+ %tmp36 = fcmp ogt float %tmp31, 0.000000e+00
+ %tmp37 = select i1 %tmp36, float %tmp33, float %tmp35
+ %max.0.i = call float @llvm.maxnum.f32(float %tmp13, float 0.000000e+00)
+ %clamp.i = call float @llvm.minnum.f32(float %max.0.i, float 1.000000e+00)
+ %max.0.i5 = call float @llvm.maxnum.f32(float %tmp21, float 0.000000e+00)
+ %clamp.i6 = call float @llvm.minnum.f32(float %max.0.i5, float 1.000000e+00)
+ %max.0.i3 = call float @llvm.maxnum.f32(float %tmp29, float 0.000000e+00)
+ %clamp.i4 = call float @llvm.minnum.f32(float %max.0.i3, float 1.000000e+00)
+ %max.0.i1 = call float @llvm.maxnum.f32(float %tmp37, float 0.000000e+00)
+ %clamp.i2 = call float @llvm.minnum.f32(float %max.0.i1, float 1.000000e+00)
+ %tmp38 = insertelement <4 x float> undef, float %clamp.i, i32 0
+ %tmp39 = insertelement <4 x float> %tmp38, float %clamp.i6, i32 1
+ %tmp40 = insertelement <4 x float> %tmp39, float %clamp.i4, i32 2
+ %tmp41 = insertelement <4 x float> %tmp40, float %clamp.i2, i32 3
+ call void @llvm.r600.store.swizzle(<4 x float> %tmp41, i32 0, i32 0)
ret void
}
-declare float @llvm.AMDGPU.clamp.f32(float, float, float) readnone
-declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
+declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) #0
+declare float @llvm.minnum.f32(float, float) #1
+declare float @llvm.maxnum.f32(float, float) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll?rev=295788&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll (removed)
@@ -1,56 +0,0 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-declare float @llvm.fabs.f32(float) nounwind readnone
-declare float @llvm.AMDGPU.clamp.f32(float, float, float) nounwind readnone
-
-; FUNC-LABEL: {{^}}clamp_0_1_f32:
-; SI: s_load_dword [[ARG:s[0-9]+]],
-; SI: v_max_f32_e64 [[RESULT:v[0-9]+]], [[ARG]], [[ARG]] clamp{{$}}
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-
-; EG: MOV_SAT
-define void @clamp_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
- %clamp = call float @llvm.AMDGPU.clamp.f32(float %src, float 0.0, float 1.0) nounwind readnone
- store float %clamp, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}clamp_fabs_0_1_f32:
-; SI: s_load_dword [[ARG:s[0-9]+]],
-; SI: v_max_f32_e64 [[RESULT:v[0-9]+]], |[[ARG]]|, |[[ARG]]| clamp{{$}}
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @clamp_fabs_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
- %src.fabs = call float @llvm.fabs.f32(float %src) nounwind readnone
- %clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fabs, float 0.0, float 1.0) nounwind readnone
- store float %clamp, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}clamp_fneg_0_1_f32:
-; SI: s_load_dword [[ARG:s[0-9]+]],
-; SI: v_max_f32_e64 [[RESULT:v[0-9]+]], -[[ARG]], -[[ARG]] clamp{{$}}
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @clamp_fneg_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
- %src.fneg = fsub float -0.0, %src
- %clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fneg, float 0.0, float 1.0) nounwind readnone
- store float %clamp, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}clamp_fneg_fabs_0_1_f32:
-; SI: s_load_dword [[ARG:s[0-9]+]],
-; SI: v_max_f32_e64 [[RESULT:v[0-9]+]], -|[[ARG]]|, -|[[ARG]]| clamp{{$}}
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @clamp_fneg_fabs_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
- %src.fabs = call float @llvm.fabs.f32(float %src) nounwind readnone
- %src.fneg.fabs = fsub float -0.0, %src.fabs
- %clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fneg.fabs, float 0.0, float 1.0) nounwind readnone
- store float %clamp, float addrspace(1)* %out, align 4
- ret void
-}
Modified: llvm/trunk/test/CodeGen/AMDGPU/pv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/pv.ll?rev=295789&r1=295788&r2=295789&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/pv.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/pv.ll Tue Feb 21 17:46:04 2017
@@ -1,240 +1,236 @@
-; RUN: llc < %s -march=r600 | FileCheck %s
+; RUN: llc -march=r600 < %s | FileCheck %s
; CHECK: DOT4 * T{{[0-9]\.W}} (MASKED)
; CHECK: MAX T{{[0-9].[XYZW]}}, 0.0, PV.X
-
define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7) {
main_body:
- %0 = extractelement <4 x float> %reg1, i32 0
- %1 = extractelement <4 x float> %reg1, i32 1
- %2 = extractelement <4 x float> %reg1, i32 2
- %3 = extractelement <4 x float> %reg1, i32 3
- %4 = extractelement <4 x float> %reg2, i32 0
- %5 = extractelement <4 x float> %reg2, i32 1
- %6 = extractelement <4 x float> %reg2, i32 2
- %7 = extractelement <4 x float> %reg2, i32 3
- %8 = extractelement <4 x float> %reg3, i32 0
- %9 = extractelement <4 x float> %reg3, i32 1
- %10 = extractelement <4 x float> %reg3, i32 2
- %11 = extractelement <4 x float> %reg3, i32 3
- %12 = extractelement <4 x float> %reg4, i32 0
- %13 = extractelement <4 x float> %reg4, i32 1
- %14 = extractelement <4 x float> %reg4, i32 2
- %15 = extractelement <4 x float> %reg4, i32 3
- %16 = extractelement <4 x float> %reg5, i32 0
- %17 = extractelement <4 x float> %reg5, i32 1
- %18 = extractelement <4 x float> %reg5, i32 2
- %19 = extractelement <4 x float> %reg5, i32 3
- %20 = extractelement <4 x float> %reg6, i32 0
- %21 = extractelement <4 x float> %reg6, i32 1
- %22 = extractelement <4 x float> %reg6, i32 2
- %23 = extractelement <4 x float> %reg6, i32 3
- %24 = extractelement <4 x float> %reg7, i32 0
- %25 = extractelement <4 x float> %reg7, i32 1
- %26 = extractelement <4 x float> %reg7, i32 2
- %27 = extractelement <4 x float> %reg7, i32 3
- %28 = load <4 x float>, <4 x float> addrspace(8)* null
- %29 = extractelement <4 x float> %28, i32 0
- %30 = fmul float %0, %29
- %31 = load <4 x float>, <4 x float> addrspace(8)* null
- %32 = extractelement <4 x float> %31, i32 1
- %33 = fmul float %0, %32
- %34 = load <4 x float>, <4 x float> addrspace(8)* null
- %35 = extractelement <4 x float> %34, i32 2
- %36 = fmul float %0, %35
- %37 = load <4 x float>, <4 x float> addrspace(8)* null
- %38 = extractelement <4 x float> %37, i32 3
- %39 = fmul float %0, %38
- %40 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %41 = extractelement <4 x float> %40, i32 0
- %42 = fmul float %1, %41
- %43 = fadd float %42, %30
- %44 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %45 = extractelement <4 x float> %44, i32 1
- %46 = fmul float %1, %45
- %47 = fadd float %46, %33
- %48 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %49 = extractelement <4 x float> %48, i32 2
- %50 = fmul float %1, %49
- %51 = fadd float %50, %36
- %52 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %53 = extractelement <4 x float> %52, i32 3
- %54 = fmul float %1, %53
- %55 = fadd float %54, %39
- %56 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %57 = extractelement <4 x float> %56, i32 0
- %58 = fmul float %2, %57
- %59 = fadd float %58, %43
- %60 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %61 = extractelement <4 x float> %60, i32 1
- %62 = fmul float %2, %61
- %63 = fadd float %62, %47
- %64 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %65 = extractelement <4 x float> %64, i32 2
- %66 = fmul float %2, %65
- %67 = fadd float %66, %51
- %68 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %69 = extractelement <4 x float> %68, i32 3
- %70 = fmul float %2, %69
- %71 = fadd float %70, %55
- %72 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
- %73 = extractelement <4 x float> %72, i32 0
- %74 = fmul float %3, %73
- %75 = fadd float %74, %59
- %76 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
- %77 = extractelement <4 x float> %76, i32 1
- %78 = fmul float %3, %77
- %79 = fadd float %78, %63
- %80 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
- %81 = extractelement <4 x float> %80, i32 2
- %82 = fmul float %3, %81
- %83 = fadd float %82, %67
- %84 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
- %85 = extractelement <4 x float> %84, i32 3
- %86 = fmul float %3, %85
- %87 = fadd float %86, %71
- %88 = insertelement <4 x float> undef, float %4, i32 0
- %89 = insertelement <4 x float> %88, float %5, i32 1
- %90 = insertelement <4 x float> %89, float %6, i32 2
- %91 = insertelement <4 x float> %90, float 0.000000e+00, i32 3
- %92 = insertelement <4 x float> undef, float %4, i32 0
- %93 = insertelement <4 x float> %92, float %5, i32 1
- %94 = insertelement <4 x float> %93, float %6, i32 2
- %95 = insertelement <4 x float> %94, float 0.000000e+00, i32 3
- %96 = call float @llvm.r600.dot4(<4 x float> %91, <4 x float> %95)
- %97 = call float @llvm.fabs.f32(float %96)
- %98 = call float @llvm.r600.recipsqrt.clamped.f32(float %97)
- %99 = fmul float %4, %98
- %100 = fmul float %5, %98
- %101 = fmul float %6, %98
- %102 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
- %103 = extractelement <4 x float> %102, i32 0
- %104 = fmul float %103, %8
- %105 = fadd float %104, %20
- %106 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
- %107 = extractelement <4 x float> %106, i32 1
- %108 = fmul float %107, %9
- %109 = fadd float %108, %21
- %110 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
- %111 = extractelement <4 x float> %110, i32 2
- %112 = fmul float %111, %10
- %113 = fadd float %112, %22
- %114 = call float @llvm.AMDGPU.clamp.f32(float %105, float 0.000000e+00, float 1.000000e+00)
- %115 = call float @llvm.AMDGPU.clamp.f32(float %109, float 0.000000e+00, float 1.000000e+00)
- %116 = call float @llvm.AMDGPU.clamp.f32(float %113, float 0.000000e+00, float 1.000000e+00)
- %117 = call float @llvm.AMDGPU.clamp.f32(float %15, float 0.000000e+00, float 1.000000e+00)
- %118 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
- %119 = extractelement <4 x float> %118, i32 0
- %120 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
- %121 = extractelement <4 x float> %120, i32 1
- %122 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
- %123 = extractelement <4 x float> %122, i32 2
- %124 = insertelement <4 x float> undef, float %99, i32 0
- %125 = insertelement <4 x float> %124, float %100, i32 1
- %126 = insertelement <4 x float> %125, float %101, i32 2
- %127 = insertelement <4 x float> %126, float 0.000000e+00, i32 3
- %128 = insertelement <4 x float> undef, float %119, i32 0
- %129 = insertelement <4 x float> %128, float %121, i32 1
- %130 = insertelement <4 x float> %129, float %123, i32 2
- %131 = insertelement <4 x float> %130, float 0.000000e+00, i32 3
- %132 = call float @llvm.r600.dot4(<4 x float> %127, <4 x float> %131)
- %133 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
- %134 = extractelement <4 x float> %133, i32 0
- %135 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
- %136 = extractelement <4 x float> %135, i32 1
- %137 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
- %138 = extractelement <4 x float> %137, i32 2
- %139 = insertelement <4 x float> undef, float %99, i32 0
- %140 = insertelement <4 x float> %139, float %100, i32 1
- %141 = insertelement <4 x float> %140, float %101, i32 2
- %142 = insertelement <4 x float> %141, float 0.000000e+00, i32 3
- %143 = insertelement <4 x float> undef, float %134, i32 0
- %144 = insertelement <4 x float> %143, float %136, i32 1
- %145 = insertelement <4 x float> %144, float %138, i32 2
- %146 = insertelement <4 x float> %145, float 0.000000e+00, i32 3
- %147 = call float @llvm.r600.dot4(<4 x float> %142, <4 x float> %146)
- %148 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
- %149 = extractelement <4 x float> %148, i32 0
- %150 = fmul float %149, %8
- %151 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
- %152 = extractelement <4 x float> %151, i32 1
- %153 = fmul float %152, %9
- %154 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
- %155 = extractelement <4 x float> %154, i32 2
- %156 = fmul float %155, %10
- %157 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
- %158 = extractelement <4 x float> %157, i32 0
- %159 = fmul float %158, %12
- %160 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
- %161 = extractelement <4 x float> %160, i32 1
- %162 = fmul float %161, %13
- %163 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
- %164 = extractelement <4 x float> %163, i32 2
- %165 = fmul float %164, %14
- %166 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
- %167 = extractelement <4 x float> %166, i32 0
- %168 = fmul float %167, %16
- %169 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
- %170 = extractelement <4 x float> %169, i32 1
- %171 = fmul float %170, %17
- %172 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
- %173 = extractelement <4 x float> %172, i32 2
- %174 = fmul float %173, %18
- %175 = fcmp uge float %132, 0.000000e+00
- %176 = select i1 %175, float %132, float 0.000000e+00
- %177 = fcmp uge float %147, 0.000000e+00
- %178 = select i1 %177, float %147, float 0.000000e+00
- %179 = call float @llvm.pow.f32(float %178, float %24)
- %180 = fcmp ult float %132, 0.000000e+00
- %181 = select i1 %180, float 0.000000e+00, float %179
- %182 = fadd float %150, %105
- %183 = fadd float %153, %109
- %184 = fadd float %156, %113
- %185 = fmul float %176, %159
- %186 = fadd float %185, %182
- %187 = fmul float %176, %162
- %188 = fadd float %187, %183
- %189 = fmul float %176, %165
- %190 = fadd float %189, %184
- %191 = fmul float %181, %168
- %192 = fadd float %191, %186
- %193 = fmul float %181, %171
- %194 = fadd float %193, %188
- %195 = fmul float %181, %174
- %196 = fadd float %195, %190
- %197 = call float @llvm.AMDGPU.clamp.f32(float %192, float 0.000000e+00, float 1.000000e+00)
- %198 = call float @llvm.AMDGPU.clamp.f32(float %194, float 0.000000e+00, float 1.000000e+00)
- %199 = call float @llvm.AMDGPU.clamp.f32(float %196, float 0.000000e+00, float 1.000000e+00)
- %200 = insertelement <4 x float> undef, float %75, i32 0
- %201 = insertelement <4 x float> %200, float %79, i32 1
- %202 = insertelement <4 x float> %201, float %83, i32 2
- %203 = insertelement <4 x float> %202, float %87, i32 3
- call void @llvm.r600.store.swizzle(<4 x float> %203, i32 60, i32 1)
- %204 = insertelement <4 x float> undef, float %197, i32 0
- %205 = insertelement <4 x float> %204, float %198, i32 1
- %206 = insertelement <4 x float> %205, float %199, i32 2
- %207 = insertelement <4 x float> %206, float %117, i32 3
- call void @llvm.r600.store.swizzle(<4 x float> %207, i32 0, i32 2)
+ %tmp = extractelement <4 x float> %reg1, i32 0
+ %tmp13 = extractelement <4 x float> %reg1, i32 1
+ %tmp14 = extractelement <4 x float> %reg1, i32 2
+ %tmp15 = extractelement <4 x float> %reg1, i32 3
+ %tmp16 = extractelement <4 x float> %reg2, i32 0
+ %tmp17 = extractelement <4 x float> %reg2, i32 1
+ %tmp18 = extractelement <4 x float> %reg2, i32 2
+ %tmp19 = extractelement <4 x float> %reg2, i32 3
+ %tmp20 = extractelement <4 x float> %reg3, i32 0
+ %tmp21 = extractelement <4 x float> %reg3, i32 1
+ %tmp22 = extractelement <4 x float> %reg3, i32 2
+ %tmp23 = extractelement <4 x float> %reg3, i32 3
+ %tmp24 = extractelement <4 x float> %reg4, i32 0
+ %tmp25 = extractelement <4 x float> %reg4, i32 1
+ %tmp26 = extractelement <4 x float> %reg4, i32 2
+ %tmp27 = extractelement <4 x float> %reg4, i32 3
+ %tmp28 = extractelement <4 x float> %reg5, i32 0
+ %tmp29 = extractelement <4 x float> %reg5, i32 1
+ %tmp30 = extractelement <4 x float> %reg5, i32 2
+ %tmp31 = extractelement <4 x float> %reg5, i32 3
+ %tmp32 = extractelement <4 x float> %reg6, i32 0
+ %tmp33 = extractelement <4 x float> %reg6, i32 1
+ %tmp34 = extractelement <4 x float> %reg6, i32 2
+ %tmp35 = extractelement <4 x float> %reg6, i32 3
+ %tmp36 = extractelement <4 x float> %reg7, i32 0
+ %tmp37 = extractelement <4 x float> %reg7, i32 1
+ %tmp38 = extractelement <4 x float> %reg7, i32 2
+ %tmp39 = extractelement <4 x float> %reg7, i32 3
+ %tmp40 = load <4 x float>, <4 x float> addrspace(8)* null
+ %tmp41 = extractelement <4 x float> %tmp40, i32 0
+ %tmp42 = fmul float %tmp, %tmp41
+ %tmp43 = load <4 x float>, <4 x float> addrspace(8)* null
+ %tmp44 = extractelement <4 x float> %tmp43, i32 1
+ %tmp45 = fmul float %tmp, %tmp44
+ %tmp46 = load <4 x float>, <4 x float> addrspace(8)* null
+ %tmp47 = extractelement <4 x float> %tmp46, i32 2
+ %tmp48 = fmul float %tmp, %tmp47
+ %tmp49 = load <4 x float>, <4 x float> addrspace(8)* null
+ %tmp50 = extractelement <4 x float> %tmp49, i32 3
+ %tmp51 = fmul float %tmp, %tmp50
+ %tmp52 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+ %tmp53 = extractelement <4 x float> %tmp52, i32 0
+ %tmp54 = fmul float %tmp13, %tmp53
+ %tmp55 = fadd float %tmp54, %tmp42
+ %tmp56 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+ %tmp57 = extractelement <4 x float> %tmp56, i32 1
+ %tmp58 = fmul float %tmp13, %tmp57
+ %tmp59 = fadd float %tmp58, %tmp45
+ %tmp60 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+ %tmp61 = extractelement <4 x float> %tmp60, i32 2
+ %tmp62 = fmul float %tmp13, %tmp61
+ %tmp63 = fadd float %tmp62, %tmp48
+ %tmp64 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+ %tmp65 = extractelement <4 x float> %tmp64, i32 3
+ %tmp66 = fmul float %tmp13, %tmp65
+ %tmp67 = fadd float %tmp66, %tmp51
+ %tmp68 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+ %tmp69 = extractelement <4 x float> %tmp68, i32 0
+ %tmp70 = fmul float %tmp14, %tmp69
+ %tmp71 = fadd float %tmp70, %tmp55
+ %tmp72 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+ %tmp73 = extractelement <4 x float> %tmp72, i32 1
+ %tmp74 = fmul float %tmp14, %tmp73
+ %tmp75 = fadd float %tmp74, %tmp59
+ %tmp76 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+ %tmp77 = extractelement <4 x float> %tmp76, i32 2
+ %tmp78 = fmul float %tmp14, %tmp77
+ %tmp79 = fadd float %tmp78, %tmp63
+ %tmp80 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
+ %tmp81 = extractelement <4 x float> %tmp80, i32 3
+ %tmp82 = fmul float %tmp14, %tmp81
+ %tmp83 = fadd float %tmp82, %tmp67
+ %tmp84 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+ %tmp85 = extractelement <4 x float> %tmp84, i32 0
+ %tmp86 = fmul float %tmp15, %tmp85
+ %tmp87 = fadd float %tmp86, %tmp71
+ %tmp88 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+ %tmp89 = extractelement <4 x float> %tmp88, i32 1
+ %tmp90 = fmul float %tmp15, %tmp89
+ %tmp91 = fadd float %tmp90, %tmp75
+ %tmp92 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+ %tmp93 = extractelement <4 x float> %tmp92, i32 2
+ %tmp94 = fmul float %tmp15, %tmp93
+ %tmp95 = fadd float %tmp94, %tmp79
+ %tmp96 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
+ %tmp97 = extractelement <4 x float> %tmp96, i32 3
+ %tmp98 = fmul float %tmp15, %tmp97
+ %tmp99 = fadd float %tmp98, %tmp83
+ %tmp100 = insertelement <4 x float> undef, float %tmp16, i32 0
+ %tmp101 = insertelement <4 x float> %tmp100, float %tmp17, i32 1
+ %tmp102 = insertelement <4 x float> %tmp101, float %tmp18, i32 2
+ %tmp103 = insertelement <4 x float> %tmp102, float 0.000000e+00, i32 3
+ %tmp104 = insertelement <4 x float> undef, float %tmp16, i32 0
+ %tmp105 = insertelement <4 x float> %tmp104, float %tmp17, i32 1
+ %tmp106 = insertelement <4 x float> %tmp105, float %tmp18, i32 2
+ %tmp107 = insertelement <4 x float> %tmp106, float 0.000000e+00, i32 3
+ %tmp108 = call float @llvm.r600.dot4(<4 x float> %tmp103, <4 x float> %tmp107)
+ %tmp109 = call float @llvm.fabs.f32(float %tmp108)
+ %tmp110 = call float @llvm.r600.recipsqrt.clamped.f32(float %tmp109)
+ %tmp111 = fmul float %tmp16, %tmp110
+ %tmp112 = fmul float %tmp17, %tmp110
+ %tmp113 = fmul float %tmp18, %tmp110
+ %tmp114 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
+ %tmp115 = extractelement <4 x float> %tmp114, i32 0
+ %tmp116 = fmul float %tmp115, %tmp20
+ %tmp117 = fadd float %tmp116, %tmp32
+ %tmp118 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
+ %tmp119 = extractelement <4 x float> %tmp118, i32 1
+ %tmp120 = fmul float %tmp119, %tmp21
+ %tmp121 = fadd float %tmp120, %tmp33
+ %tmp122 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
+ %tmp123 = extractelement <4 x float> %tmp122, i32 2
+ %tmp124 = fmul float %tmp123, %tmp22
+ %tmp125 = fadd float %tmp124, %tmp34
+ %max.0.i = call float @llvm.maxnum.f32(float %tmp117, float 0.000000e+00)
+ %clamp.i = call float @llvm.minnum.f32(float %max.0.i, float 1.000000e+00)
+ %max.0.i11 = call float @llvm.maxnum.f32(float %tmp121, float 0.000000e+00)
+ %clamp.i12 = call float @llvm.minnum.f32(float %max.0.i11, float 1.000000e+00)
+ %max.0.i9 = call float @llvm.maxnum.f32(float %tmp125, float 0.000000e+00)
+ %clamp.i10 = call float @llvm.minnum.f32(float %max.0.i9, float 1.000000e+00)
+ %max.0.i7 = call float @llvm.maxnum.f32(float %tmp27, float 0.000000e+00)
+ %clamp.i8 = call float @llvm.minnum.f32(float %max.0.i7, float 1.000000e+00)
+ %tmp126 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
+ %tmp127 = extractelement <4 x float> %tmp126, i32 0
+ %tmp128 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
+ %tmp129 = extractelement <4 x float> %tmp128, i32 1
+ %tmp130 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
+ %tmp131 = extractelement <4 x float> %tmp130, i32 2
+ %tmp132 = insertelement <4 x float> undef, float %tmp111, i32 0
+ %tmp133 = insertelement <4 x float> %tmp132, float %tmp112, i32 1
+ %tmp134 = insertelement <4 x float> %tmp133, float %tmp113, i32 2
+ %tmp135 = insertelement <4 x float> %tmp134, float 0.000000e+00, i32 3
+ %tmp136 = insertelement <4 x float> undef, float %tmp127, i32 0
+ %tmp137 = insertelement <4 x float> %tmp136, float %tmp129, i32 1
+ %tmp138 = insertelement <4 x float> %tmp137, float %tmp131, i32 2
+ %tmp139 = insertelement <4 x float> %tmp138, float 0.000000e+00, i32 3
+ %tmp140 = call float @llvm.r600.dot4(<4 x float> %tmp135, <4 x float> %tmp139)
+ %tmp141 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
+ %tmp142 = extractelement <4 x float> %tmp141, i32 0
+ %tmp143 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
+ %tmp144 = extractelement <4 x float> %tmp143, i32 1
+ %tmp145 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
+ %tmp146 = extractelement <4 x float> %tmp145, i32 2
+ %tmp147 = insertelement <4 x float> undef, float %tmp111, i32 0
+ %tmp148 = insertelement <4 x float> %tmp147, float %tmp112, i32 1
+ %tmp149 = insertelement <4 x float> %tmp148, float %tmp113, i32 2
+ %tmp150 = insertelement <4 x float> %tmp149, float 0.000000e+00, i32 3
+ %tmp151 = insertelement <4 x float> undef, float %tmp142, i32 0
+ %tmp152 = insertelement <4 x float> %tmp151, float %tmp144, i32 1
+ %tmp153 = insertelement <4 x float> %tmp152, float %tmp146, i32 2
+ %tmp154 = insertelement <4 x float> %tmp153, float 0.000000e+00, i32 3
+ %tmp155 = call float @llvm.r600.dot4(<4 x float> %tmp150, <4 x float> %tmp154)
+ %tmp156 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
+ %tmp157 = extractelement <4 x float> %tmp156, i32 0
+ %tmp158 = fmul float %tmp157, %tmp20
+ %tmp159 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
+ %tmp160 = extractelement <4 x float> %tmp159, i32 1
+ %tmp161 = fmul float %tmp160, %tmp21
+ %tmp162 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
+ %tmp163 = extractelement <4 x float> %tmp162, i32 2
+ %tmp164 = fmul float %tmp163, %tmp22
+ %tmp165 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
+ %tmp166 = extractelement <4 x float> %tmp165, i32 0
+ %tmp167 = fmul float %tmp166, %tmp24
+ %tmp168 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
+ %tmp169 = extractelement <4 x float> %tmp168, i32 1
+ %tmp170 = fmul float %tmp169, %tmp25
+ %tmp171 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
+ %tmp172 = extractelement <4 x float> %tmp171, i32 2
+ %tmp173 = fmul float %tmp172, %tmp26
+ %tmp174 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
+ %tmp175 = extractelement <4 x float> %tmp174, i32 0
+ %tmp176 = fmul float %tmp175, %tmp28
+ %tmp177 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
+ %tmp178 = extractelement <4 x float> %tmp177, i32 1
+ %tmp179 = fmul float %tmp178, %tmp29
+ %tmp180 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
+ %tmp181 = extractelement <4 x float> %tmp180, i32 2
+ %tmp182 = fmul float %tmp181, %tmp30
+ %tmp183 = fcmp uge float %tmp140, 0.000000e+00
+ %tmp184 = select i1 %tmp183, float %tmp140, float 0.000000e+00
+ %tmp185 = fcmp uge float %tmp155, 0.000000e+00
+ %tmp186 = select i1 %tmp185, float %tmp155, float 0.000000e+00
+ %tmp187 = call float @llvm.pow.f32(float %tmp186, float %tmp36)
+ %tmp188 = fcmp ult float %tmp140, 0.000000e+00
+ %tmp189 = select i1 %tmp188, float 0.000000e+00, float %tmp187
+ %tmp190 = fadd float %tmp158, %tmp117
+ %tmp191 = fadd float %tmp161, %tmp121
+ %tmp192 = fadd float %tmp164, %tmp125
+ %tmp193 = fmul float %tmp184, %tmp167
+ %tmp194 = fadd float %tmp193, %tmp190
+ %tmp195 = fmul float %tmp184, %tmp170
+ %tmp196 = fadd float %tmp195, %tmp191
+ %tmp197 = fmul float %tmp184, %tmp173
+ %tmp198 = fadd float %tmp197, %tmp192
+ %tmp199 = fmul float %tmp189, %tmp176
+ %tmp200 = fadd float %tmp199, %tmp194
+ %tmp201 = fmul float %tmp189, %tmp179
+ %tmp202 = fadd float %tmp201, %tmp196
+ %tmp203 = fmul float %tmp189, %tmp182
+ %tmp204 = fadd float %tmp203, %tmp198
+ %max.0.i5 = call float @llvm.maxnum.f32(float %tmp200, float 0.000000e+00)
+ %clamp.i6 = call float @llvm.minnum.f32(float %max.0.i5, float 1.000000e+00)
+ %max.0.i3 = call float @llvm.maxnum.f32(float %tmp202, float 0.000000e+00)
+ %clamp.i4 = call float @llvm.minnum.f32(float %max.0.i3, float 1.000000e+00)
+ %max.0.i1 = call float @llvm.maxnum.f32(float %tmp204, float 0.000000e+00)
+ %clamp.i2 = call float @llvm.minnum.f32(float %max.0.i1, float 1.000000e+00)
+ %tmp205 = insertelement <4 x float> undef, float %tmp87, i32 0
+ %tmp206 = insertelement <4 x float> %tmp205, float %tmp91, i32 1
+ %tmp207 = insertelement <4 x float> %tmp206, float %tmp95, i32 2
+ %tmp208 = insertelement <4 x float> %tmp207, float %tmp99, i32 3
+ call void @llvm.r600.store.swizzle(<4 x float> %tmp208, i32 60, i32 1)
+ %tmp209 = insertelement <4 x float> undef, float %clamp.i6, i32 0
+ %tmp210 = insertelement <4 x float> %tmp209, float %clamp.i4, i32 1
+ %tmp211 = insertelement <4 x float> %tmp210, float %clamp.i2, i32 2
+ %tmp212 = insertelement <4 x float> %tmp211, float %clamp.i8, i32 3
+ call void @llvm.r600.store.swizzle(<4 x float> %tmp212, i32 0, i32 2)
ret void
}
-; Function Attrs: readnone
-declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #1
-
-; Function Attrs: readonly
-declare float @llvm.fabs.f32(float) #1
-
-; Function Attrs: readnone
-declare float @llvm.r600.recipsqrt.clamped.f32(float) #1
-
-; Function Attrs: readnone
-declare float @llvm.AMDGPU.clamp.f32(float, float, float) #1
-
-; Function Attrs: nounwind readonly
-declare float @llvm.pow.f32(float, float) #2
-
-declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) #3
+declare float @llvm.minnum.f32(float, float) #0
+declare float @llvm.maxnum.f32(float, float) #0
+declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #0
+declare float @llvm.fabs.f32(float) #0
+declare float @llvm.r600.recipsqrt.clamped.f32(float) #0
+declare float @llvm.pow.f32(float, float) #0
+declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) #1
-attributes #1 = { nounwind readnone }
-attributes #2 = { nounwind readonly }
-attributes #3 = { nounwind }
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind }
Modified: llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll?rev=295789&r1=295788&r2=295789&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll Tue Feb 21 17:46:04 2017
@@ -1,81 +1,85 @@
-;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
-;REQUIRES: asserts
+; RUN: llc -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs < %s
+; REQUIRES: asserts
-define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
+define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
main_body:
- %0 = extractelement <4 x float> %reg1, i32 0
- %1 = extractelement <4 x float> %reg1, i32 1
- %2 = extractelement <4 x float> %reg1, i32 2
- %3 = extractelement <4 x float> %reg1, i32 3
- %4 = fcmp ult float %1, 0.000000e+00
- %5 = select i1 %4, float 1.000000e+00, float 0.000000e+00
- %6 = fsub float -0.000000e+00, %5
- %7 = fptosi float %6 to i32
- %8 = bitcast i32 %7 to float
- %9 = fcmp ult float %0, 5.700000e+01
- %10 = select i1 %9, float 1.000000e+00, float 0.000000e+00
- %11 = fsub float -0.000000e+00, %10
- %12 = fptosi float %11 to i32
- %13 = bitcast i32 %12 to float
- %14 = bitcast float %8 to i32
- %15 = bitcast float %13 to i32
- %16 = and i32 %14, %15
- %17 = bitcast i32 %16 to float
- %18 = bitcast float %17 to i32
- %19 = icmp ne i32 %18, 0
- %20 = fcmp ult float %0, 0.000000e+00
- %21 = select i1 %20, float 1.000000e+00, float 0.000000e+00
- %22 = fsub float -0.000000e+00, %21
- %23 = fptosi float %22 to i32
- %24 = bitcast i32 %23 to float
- %25 = bitcast float %24 to i32
- %26 = icmp ne i32 %25, 0
- br i1 %19, label %IF, label %ELSE
+ %tmp = extractelement <4 x float> %reg1, i32 0
+ %tmp5 = extractelement <4 x float> %reg1, i32 1
+ %tmp6 = extractelement <4 x float> %reg1, i32 2
+ %tmp7 = extractelement <4 x float> %reg1, i32 3
+ %tmp8 = fcmp ult float %tmp5, 0.000000e+00
+ %tmp9 = select i1 %tmp8, float 1.000000e+00, float 0.000000e+00
+ %tmp10 = fsub float -0.000000e+00, %tmp9
+ %tmp11 = fptosi float %tmp10 to i32
+ %tmp12 = bitcast i32 %tmp11 to float
+ %tmp13 = fcmp ult float %tmp, 5.700000e+01
+ %tmp14 = select i1 %tmp13, float 1.000000e+00, float 0.000000e+00
+ %tmp15 = fsub float -0.000000e+00, %tmp14
+ %tmp16 = fptosi float %tmp15 to i32
+ %tmp17 = bitcast i32 %tmp16 to float
+ %tmp18 = bitcast float %tmp12 to i32
+ %tmp19 = bitcast float %tmp17 to i32
+ %tmp20 = and i32 %tmp18, %tmp19
+ %tmp21 = bitcast i32 %tmp20 to float
+ %tmp22 = bitcast float %tmp21 to i32
+ %tmp23 = icmp ne i32 %tmp22, 0
+ %tmp24 = fcmp ult float %tmp, 0.000000e+00
+ %tmp25 = select i1 %tmp24, float 1.000000e+00, float 0.000000e+00
+ %tmp26 = fsub float -0.000000e+00, %tmp25
+ %tmp27 = fptosi float %tmp26 to i32
+ %tmp28 = bitcast i32 %tmp27 to float
+ %tmp29 = bitcast float %tmp28 to i32
+ %tmp30 = icmp ne i32 %tmp29, 0
+ br i1 %tmp23, label %IF, label %ELSE
IF: ; preds = %main_body
- %. = select i1 %26, float 0.000000e+00, float 1.000000e+00
- %.18 = select i1 %26, float 1.000000e+00, float 0.000000e+00
+ %. = select i1 %tmp30, float 0.000000e+00, float 1.000000e+00
+ %.18 = select i1 %tmp30, float 1.000000e+00, float 0.000000e+00
br label %ENDIF
ELSE: ; preds = %main_body
- br i1 %26, label %ENDIF, label %ELSE17
+ br i1 %tmp30, label %ENDIF, label %ELSE17
ENDIF: ; preds = %ELSE17, %ELSE, %IF
- %temp1.0 = phi float [ %., %IF ], [ %48, %ELSE17 ], [ 0.000000e+00, %ELSE ]
- %temp2.0 = phi float [ 0.000000e+00, %IF ], [ %49, %ELSE17 ], [ 1.000000e+00, %ELSE ]
- %temp.0 = phi float [ %.18, %IF ], [ %47, %ELSE17 ], [ 0.000000e+00, %ELSE ]
- %27 = call float @llvm.AMDGPU.clamp.f32(float %temp.0, float 0.000000e+00, float 1.000000e+00)
- %28 = call float @llvm.AMDGPU.clamp.f32(float %temp1.0, float 0.000000e+00, float 1.000000e+00)
- %29 = call float @llvm.AMDGPU.clamp.f32(float %temp2.0, float 0.000000e+00, float 1.000000e+00)
- %30 = call float @llvm.AMDGPU.clamp.f32(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
- %31 = insertelement <4 x float> undef, float %27, i32 0
- %32 = insertelement <4 x float> %31, float %28, i32 1
- %33 = insertelement <4 x float> %32, float %29, i32 2
- %34 = insertelement <4 x float> %33, float %30, i32 3
- call void @llvm.r600.store.swizzle(<4 x float> %34, i32 0, i32 0)
+ %temp1.0 = phi float [ %., %IF ], [ %tmp48, %ELSE17 ], [ 0.000000e+00, %ELSE ]
+ %temp2.0 = phi float [ 0.000000e+00, %IF ], [ %tmp49, %ELSE17 ], [ 1.000000e+00, %ELSE ]
+ %temp.0 = phi float [ %.18, %IF ], [ %tmp47, %ELSE17 ], [ 0.000000e+00, %ELSE ]
+ %max.0.i = call float @llvm.maxnum.f32(float %temp.0, float 0.000000e+00)
+ %clamp.i = call float @llvm.minnum.f32(float %max.0.i, float 1.000000e+00)
+ %max.0.i3 = call float @llvm.maxnum.f32(float %temp1.0, float 0.000000e+00)
+ %clamp.i4 = call float @llvm.minnum.f32(float %max.0.i3, float 1.000000e+00)
+ %max.0.i1 = call float @llvm.maxnum.f32(float %temp2.0, float 0.000000e+00)
+ %clamp.i2 = call float @llvm.minnum.f32(float %max.0.i1, float 1.000000e+00)
+ %tmp31 = insertelement <4 x float> undef, float %clamp.i, i32 0
+ %tmp32 = insertelement <4 x float> %tmp31, float %clamp.i4, i32 1
+ %tmp33 = insertelement <4 x float> %tmp32, float %clamp.i2, i32 2
+ %tmp34 = insertelement <4 x float> %tmp33, float 1.000000e+00, i32 3
+ call void @llvm.r600.store.swizzle(<4 x float> %tmp34, i32 0, i32 0)
ret void
ELSE17: ; preds = %ELSE
- %35 = fadd float 0.000000e+00, 0x3FC99999A0000000
- %36 = fadd float 0.000000e+00, 0x3FC99999A0000000
- %37 = fadd float 0.000000e+00, 0x3FC99999A0000000
- %38 = fadd float %35, 0x3FC99999A0000000
- %39 = fadd float %36, 0x3FC99999A0000000
- %40 = fadd float %37, 0x3FC99999A0000000
- %41 = fadd float %38, 0x3FC99999A0000000
- %42 = fadd float %39, 0x3FC99999A0000000
- %43 = fadd float %40, 0x3FC99999A0000000
- %44 = fadd float %41, 0x3FC99999A0000000
- %45 = fadd float %42, 0x3FC99999A0000000
- %46 = fadd float %43, 0x3FC99999A0000000
- %47 = fadd float %44, 0x3FC99999A0000000
- %48 = fadd float %45, 0x3FC99999A0000000
- %49 = fadd float %46, 0x3FC99999A0000000
+ %tmp35 = fadd float 0.000000e+00, 0x3FC99999A0000000
+ %tmp36 = fadd float 0.000000e+00, 0x3FC99999A0000000
+ %tmp37 = fadd float 0.000000e+00, 0x3FC99999A0000000
+ %tmp38 = fadd float %tmp35, 0x3FC99999A0000000
+ %tmp39 = fadd float %tmp36, 0x3FC99999A0000000
+ %tmp40 = fadd float %tmp37, 0x3FC99999A0000000
+ %tmp41 = fadd float %tmp38, 0x3FC99999A0000000
+ %tmp42 = fadd float %tmp39, 0x3FC99999A0000000
+ %tmp43 = fadd float %tmp40, 0x3FC99999A0000000
+ %tmp44 = fadd float %tmp41, 0x3FC99999A0000000
+ %tmp45 = fadd float %tmp42, 0x3FC99999A0000000
+ %tmp46 = fadd float %tmp43, 0x3FC99999A0000000
+ %tmp47 = fadd float %tmp44, 0x3FC99999A0000000
+ %tmp48 = fadd float %tmp45, 0x3FC99999A0000000
+ %tmp49 = fadd float %tmp46, 0x3FC99999A0000000
br label %ENDIF
}
-declare float @llvm.AMDGPU.clamp.f32(float, float, float) #0
+declare float @llvm.minnum.f32(float, float) #1
+declare float @llvm.maxnum.f32(float, float) #1
declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
-attributes #0 = { readnone }
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
Modified: llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll?rev=295789&r1=295788&r2=295789&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll Tue Feb 21 17:46:04 2017
@@ -1,88 +1,91 @@
-;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
-;REQUIRES: asserts
+; RUN: llc -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs < %s
+; REQUIRES: asserts
-define void @main() {
+define void @main() #0 {
main_body:
- %0 = load <4 x float>, <4 x float> addrspace(9)* null
- %1 = extractelement <4 x float> %0, i32 3
- %2 = fptosi float %1 to i32
- %3 = bitcast i32 %2 to float
- %4 = bitcast float %3 to i32
- %5 = sdiv i32 %4, 4
- %6 = bitcast i32 %5 to float
- %7 = bitcast float %6 to i32
- %8 = mul i32 %7, 4
- %9 = bitcast i32 %8 to float
- %10 = bitcast float %9 to i32
- %11 = sub i32 0, %10
- %12 = bitcast i32 %11 to float
- %13 = bitcast float %3 to i32
- %14 = bitcast float %12 to i32
- %15 = add i32 %13, %14
- %16 = bitcast i32 %15 to float
- %17 = load <4 x float>, <4 x float> addrspace(9)* null
- %18 = extractelement <4 x float> %17, i32 0
- %19 = load <4 x float>, <4 x float> addrspace(9)* null
- %20 = extractelement <4 x float> %19, i32 1
- %21 = load <4 x float>, <4 x float> addrspace(9)* null
- %22 = extractelement <4 x float> %21, i32 2
+ %tmp = load <4 x float>, <4 x float> addrspace(9)* null
+ %tmp5 = extractelement <4 x float> %tmp, i32 3
+ %tmp6 = fptosi float %tmp5 to i32
+ %tmp7 = bitcast i32 %tmp6 to float
+ %tmp8 = bitcast float %tmp7 to i32
+ %tmp9 = sdiv i32 %tmp8, 4
+ %tmp10 = bitcast i32 %tmp9 to float
+ %tmp11 = bitcast float %tmp10 to i32
+ %tmp12 = mul i32 %tmp11, 4
+ %tmp13 = bitcast i32 %tmp12 to float
+ %tmp14 = bitcast float %tmp13 to i32
+ %tmp15 = sub i32 0, %tmp14
+ %tmp16 = bitcast i32 %tmp15 to float
+ %tmp17 = bitcast float %tmp7 to i32
+ %tmp18 = bitcast float %tmp16 to i32
+ %tmp19 = add i32 %tmp17, %tmp18
+ %tmp20 = bitcast i32 %tmp19 to float
+ %tmp21 = load <4 x float>, <4 x float> addrspace(9)* null
+ %tmp22 = extractelement <4 x float> %tmp21, i32 0
+ %tmp23 = load <4 x float>, <4 x float> addrspace(9)* null
+ %tmp24 = extractelement <4 x float> %tmp23, i32 1
+ %tmp25 = load <4 x float>, <4 x float> addrspace(9)* null
+ %tmp26 = extractelement <4 x float> %tmp25, i32 2
br label %LOOP
LOOP: ; preds = %IF31, %main_body
- %temp12.0 = phi float [ 0.000000e+00, %main_body ], [ %47, %IF31 ]
- %temp6.0 = phi float [ %22, %main_body ], [ %temp6.1, %IF31 ]
- %temp5.0 = phi float [ %20, %main_body ], [ %temp5.1, %IF31 ]
- %temp4.0 = phi float [ %18, %main_body ], [ %temp4.1, %IF31 ]
- %23 = bitcast float %temp12.0 to i32
- %24 = bitcast float %6 to i32
- %25 = icmp sge i32 %23, %24
- %26 = sext i1 %25 to i32
- %27 = bitcast i32 %26 to float
- %28 = bitcast float %27 to i32
- %29 = icmp ne i32 %28, 0
- br i1 %29, label %IF, label %LOOP29
+ %temp12.0 = phi float [ 0.000000e+00, %main_body ], [ %tmp47, %IF31 ]
+ %temp6.0 = phi float [ %tmp26, %main_body ], [ %temp6.1, %IF31 ]
+ %temp5.0 = phi float [ %tmp24, %main_body ], [ %temp5.1, %IF31 ]
+ %temp4.0 = phi float [ %tmp22, %main_body ], [ %temp4.1, %IF31 ]
+ %tmp27 = bitcast float %temp12.0 to i32
+ %tmp28 = bitcast float %tmp10 to i32
+ %tmp29 = icmp sge i32 %tmp27, %tmp28
+ %tmp30 = sext i1 %tmp29 to i32
+ %tmp31 = bitcast i32 %tmp30 to float
+ %tmp32 = bitcast float %tmp31 to i32
+ %tmp33 = icmp ne i32 %tmp32, 0
+ br i1 %tmp33, label %IF, label %LOOP29
IF: ; preds = %LOOP
- %30 = call float @llvm.AMDGPU.clamp.f32(float %temp4.0, float 0.000000e+00, float 1.000000e+00)
- %31 = call float @llvm.AMDGPU.clamp.f32(float %temp5.0, float 0.000000e+00, float 1.000000e+00)
- %32 = call float @llvm.AMDGPU.clamp.f32(float %temp6.0, float 0.000000e+00, float 1.000000e+00)
- %33 = call float @llvm.AMDGPU.clamp.f32(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
- %34 = insertelement <4 x float> undef, float %30, i32 0
- %35 = insertelement <4 x float> %34, float %31, i32 1
- %36 = insertelement <4 x float> %35, float %32, i32 2
- %37 = insertelement <4 x float> %36, float %33, i32 3
- call void @llvm.r600.store.swizzle(<4 x float> %37, i32 0, i32 0)
+ %max.0.i = call float @llvm.maxnum.f32(float %temp4.0, float 0.000000e+00)
+ %clamp.i = call float @llvm.minnum.f32(float %max.0.i, float 1.000000e+00)
+ %max.0.i3 = call float @llvm.maxnum.f32(float %temp5.0, float 0.000000e+00)
+ %clamp.i4 = call float @llvm.minnum.f32(float %max.0.i3, float 1.000000e+00)
+ %max.0.i1 = call float @llvm.maxnum.f32(float %temp6.0, float 0.000000e+00)
+ %clamp.i2 = call float @llvm.minnum.f32(float %max.0.i1, float 1.000000e+00)
+ %tmp34 = insertelement <4 x float> undef, float %clamp.i, i32 0
+ %tmp35 = insertelement <4 x float> %tmp34, float %clamp.i4, i32 1
+ %tmp36 = insertelement <4 x float> %tmp35, float %clamp.i2, i32 2
+ %tmp37 = insertelement <4 x float> %tmp36, float 1.000000e+00, i32 3
+ call void @llvm.r600.store.swizzle(<4 x float> %tmp37, i32 0, i32 0)
ret void
-LOOP29: ; preds = %LOOP, %ENDIF30
+LOOP29: ; preds = %ENDIF30, %LOOP
%temp6.1 = phi float [ %temp4.1, %ENDIF30 ], [ %temp6.0, %LOOP ]
%temp5.1 = phi float [ %temp6.1, %ENDIF30 ], [ %temp5.0, %LOOP ]
%temp4.1 = phi float [ %temp5.1, %ENDIF30 ], [ %temp4.0, %LOOP ]
- %temp20.0 = phi float [ %50, %ENDIF30 ], [ 0.000000e+00, %LOOP ]
- %38 = bitcast float %temp20.0 to i32
- %39 = bitcast float %16 to i32
- %40 = icmp sge i32 %38, %39
- %41 = sext i1 %40 to i32
- %42 = bitcast i32 %41 to float
- %43 = bitcast float %42 to i32
- %44 = icmp ne i32 %43, 0
- br i1 %44, label %IF31, label %ENDIF30
+ %temp20.0 = phi float [ %tmp50, %ENDIF30 ], [ 0.000000e+00, %LOOP ]
+ %tmp38 = bitcast float %temp20.0 to i32
+ %tmp39 = bitcast float %tmp20 to i32
+ %tmp40 = icmp sge i32 %tmp38, %tmp39
+ %tmp41 = sext i1 %tmp40 to i32
+ %tmp42 = bitcast i32 %tmp41 to float
+ %tmp43 = bitcast float %tmp42 to i32
+ %tmp44 = icmp ne i32 %tmp43, 0
+ br i1 %tmp44, label %IF31, label %ENDIF30
IF31: ; preds = %LOOP29
- %45 = bitcast float %temp12.0 to i32
- %46 = add i32 %45, 1
- %47 = bitcast i32 %46 to float
+ %tmp45 = bitcast float %temp12.0 to i32
+ %tmp46 = add i32 %tmp45, 1
+ %tmp47 = bitcast i32 %tmp46 to float
br label %LOOP
ENDIF30: ; preds = %LOOP29
- %48 = bitcast float %temp20.0 to i32
- %49 = add i32 %48, 1
- %50 = bitcast i32 %49 to float
+ %tmp48 = bitcast float %temp20.0 to i32
+ %tmp49 = add i32 %tmp48, 1
+ %tmp50 = bitcast i32 %tmp49 to float
br label %LOOP29
}
-declare float @llvm.AMDGPU.clamp.f32(float, float, float) #0
+declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) #0
+declare float @llvm.minnum.f32(float, float) #1
+declare float @llvm.maxnum.f32(float, float) #1
-declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
-
-attributes #0 = { readnone }
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
Modified: llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop.ll?rev=295789&r1=295788&r2=295789&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop.ll Tue Feb 21 17:46:04 2017
@@ -1,55 +1,84 @@
-;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
-;REQUIRES: asserts
+; RUN: llc -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs < %s
+; REQUIRES: asserts
-define void @main() {
+define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
main_body:
- %0 = load <4 x float>, <4 x float> addrspace(9)* null
- %1 = extractelement <4 x float> %0, i32 3
- %2 = fptosi float %1 to i32
- %3 = bitcast i32 %2 to float
- %4 = load <4 x float>, <4 x float> addrspace(9)* null
- %5 = extractelement <4 x float> %4, i32 0
- %6 = load <4 x float>, <4 x float> addrspace(9)* null
- %7 = extractelement <4 x float> %6, i32 1
- %8 = load <4 x float>, <4 x float> addrspace(9)* null
- %9 = extractelement <4 x float> %8, i32 2
- br label %LOOP
-
-LOOP: ; preds = %ENDIF, %main_body
- %temp4.0 = phi float [ %5, %main_body ], [ %temp5.0, %ENDIF ]
- %temp5.0 = phi float [ %7, %main_body ], [ %temp6.0, %ENDIF ]
- %temp6.0 = phi float [ %9, %main_body ], [ %temp4.0, %ENDIF ]
- %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %27, %ENDIF ]
- %10 = bitcast float %temp8.0 to i32
- %11 = bitcast float %3 to i32
- %12 = icmp sge i32 %10, %11
- %13 = sext i1 %12 to i32
- %14 = bitcast i32 %13 to float
- %15 = bitcast float %14 to i32
- %16 = icmp ne i32 %15, 0
- br i1 %16, label %IF, label %ENDIF
-
-IF: ; preds = %LOOP
- %17 = call float @llvm.AMDGPU.clamp.f32(float %temp4.0, float 0.000000e+00, float 1.000000e+00)
- %18 = call float @llvm.AMDGPU.clamp.f32(float %temp5.0, float 0.000000e+00, float 1.000000e+00)
- %19 = call float @llvm.AMDGPU.clamp.f32(float %temp6.0, float 0.000000e+00, float 1.000000e+00)
- %20 = call float @llvm.AMDGPU.clamp.f32(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
- %21 = insertelement <4 x float> undef, float %17, i32 0
- %22 = insertelement <4 x float> %21, float %18, i32 1
- %23 = insertelement <4 x float> %22, float %19, i32 2
- %24 = insertelement <4 x float> %23, float %20, i32 3
- call void @llvm.r600.store.swizzle(<4 x float> %24, i32 0, i32 0)
+ %tmp = extractelement <4 x float> %reg1, i32 0
+ %tmp5 = extractelement <4 x float> %reg1, i32 1
+ %tmp6 = extractelement <4 x float> %reg1, i32 2
+ %tmp7 = extractelement <4 x float> %reg1, i32 3
+ %tmp8 = fcmp ult float %tmp5, 0.000000e+00
+ %tmp9 = select i1 %tmp8, float 1.000000e+00, float 0.000000e+00
+ %tmp10 = fsub float -0.000000e+00, %tmp9
+ %tmp11 = fptosi float %tmp10 to i32
+ %tmp12 = bitcast i32 %tmp11 to float
+ %tmp13 = fcmp ult float %tmp, 5.700000e+01
+ %tmp14 = select i1 %tmp13, float 1.000000e+00, float 0.000000e+00
+ %tmp15 = fsub float -0.000000e+00, %tmp14
+ %tmp16 = fptosi float %tmp15 to i32
+ %tmp17 = bitcast i32 %tmp16 to float
+ %tmp18 = bitcast float %tmp12 to i32
+ %tmp19 = bitcast float %tmp17 to i32
+ %tmp20 = and i32 %tmp18, %tmp19
+ %tmp21 = bitcast i32 %tmp20 to float
+ %tmp22 = bitcast float %tmp21 to i32
+ %tmp23 = icmp ne i32 %tmp22, 0
+ %tmp24 = fcmp ult float %tmp, 0.000000e+00
+ %tmp25 = select i1 %tmp24, float 1.000000e+00, float 0.000000e+00
+ %tmp26 = fsub float -0.000000e+00, %tmp25
+ %tmp27 = fptosi float %tmp26 to i32
+ %tmp28 = bitcast i32 %tmp27 to float
+ %tmp29 = bitcast float %tmp28 to i32
+ %tmp30 = icmp ne i32 %tmp29, 0
+ br i1 %tmp23, label %IF, label %ELSE
+
+IF: ; preds = %main_body
+ %. = select i1 %tmp30, float 0.000000e+00, float 1.000000e+00
+ %.18 = select i1 %tmp30, float 1.000000e+00, float 0.000000e+00
+ br label %ENDIF
+
+ELSE: ; preds = %main_body
+ br i1 %tmp30, label %ENDIF, label %ELSE17
+
+ENDIF: ; preds = %ELSE17, %ELSE, %IF
+ %temp1.0 = phi float [ %., %IF ], [ %tmp48, %ELSE17 ], [ 0.000000e+00, %ELSE ]
+ %temp2.0 = phi float [ 0.000000e+00, %IF ], [ %tmp49, %ELSE17 ], [ 1.000000e+00, %ELSE ]
+ %temp.0 = phi float [ %.18, %IF ], [ %tmp47, %ELSE17 ], [ 0.000000e+00, %ELSE ]
+ %max.0.i = call float @llvm.maxnum.f32(float %temp.0, float 0.000000e+00)
+ %clamp.i = call float @llvm.minnum.f32(float %max.0.i, float 1.000000e+00)
+ %max.0.i3 = call float @llvm.maxnum.f32(float %temp1.0, float 0.000000e+00)
+ %clamp.i4 = call float @llvm.minnum.f32(float %max.0.i3, float 1.000000e+00)
+ %max.0.i1 = call float @llvm.maxnum.f32(float %temp2.0, float 0.000000e+00)
+ %clamp.i2 = call float @llvm.minnum.f32(float %max.0.i1, float 1.000000e+00)
+ %tmp31 = insertelement <4 x float> undef, float %clamp.i, i32 0
+ %tmp32 = insertelement <4 x float> %tmp31, float %clamp.i4, i32 1
+ %tmp33 = insertelement <4 x float> %tmp32, float %clamp.i2, i32 2
+ %tmp34 = insertelement <4 x float> %tmp33, float 1.000000e+00, i32 3
+ call void @llvm.r600.store.swizzle(<4 x float> %tmp34, i32 0, i32 0)
ret void
-ENDIF: ; preds = %LOOP
- %25 = bitcast float %temp8.0 to i32
- %26 = add i32 %25, 1
- %27 = bitcast i32 %26 to float
- br label %LOOP
+ELSE17: ; preds = %ELSE
+ %tmp35 = fadd float 0.000000e+00, 0x3FC99999A0000000
+ %tmp36 = fadd float 0.000000e+00, 0x3FC99999A0000000
+ %tmp37 = fadd float 0.000000e+00, 0x3FC99999A0000000
+ %tmp38 = fadd float %tmp35, 0x3FC99999A0000000
+ %tmp39 = fadd float %tmp36, 0x3FC99999A0000000
+ %tmp40 = fadd float %tmp37, 0x3FC99999A0000000
+ %tmp41 = fadd float %tmp38, 0x3FC99999A0000000
+ %tmp42 = fadd float %tmp39, 0x3FC99999A0000000
+ %tmp43 = fadd float %tmp40, 0x3FC99999A0000000
+ %tmp44 = fadd float %tmp41, 0x3FC99999A0000000
+ %tmp45 = fadd float %tmp42, 0x3FC99999A0000000
+ %tmp46 = fadd float %tmp43, 0x3FC99999A0000000
+ %tmp47 = fadd float %tmp44, 0x3FC99999A0000000
+ %tmp48 = fadd float %tmp45, 0x3FC99999A0000000
+ %tmp49 = fadd float %tmp46, 0x3FC99999A0000000
+ br label %ENDIF
}
-declare float @llvm.AMDGPU.clamp.f32(float, float, float) #0
+declare float @llvm.minnum.f32(float, float) #1
+declare float @llvm.maxnum.f32(float, float) #1
+declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) #0
-declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
-
-attributes #0 = { readnone }
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
Modified: llvm/trunk/test/CodeGen/AMDGPU/si-sgpr-spill.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/si-sgpr-spill.ll?rev=295789&r1=295788&r2=295789&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/si-sgpr-spill.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/si-sgpr-spill.ll Tue Feb 21 17:46:04 2017
@@ -1,28 +1,28 @@
-; RUN: llc -march=amdgcn -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=TOVGPR %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+vgpr-spilling,-mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK %s
+; RUN: llc -march=amdgcn -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=TOVGPR %s
+; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+vgpr-spilling,-mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; These tests check that the compiler won't crash when it needs to spill
; SGPRs.
@ddxy_lds = external addrspace(3) global [64 x i32]
-; CHECK-LABEL: {{^}}main:
-; CHECK: s_wqm
+; GCN-LABEL: {{^}}main:
+; GCN: s_wqm
; Make sure not emitting unused scratch resource descriptor setup
-; CHECK-NOT: s_mov_b32
-; CHECK-NOT: s_mov_b32
-; CHECK-NOT: s_mov_b32
-; CHECK-NOT: s_mov_b32
+; GCN-NOT: s_mov_b32
+; GCN-NOT: s_mov_b32
+; GCN-NOT: s_mov_b32
+; GCN-NOT: s_mov_b32
-; CHECK: s_mov_b32 m0
+; GCN: s_mov_b32 m0
; Make sure scratch space isn't being used for SGPR->VGPR spills
; FIXME: Seem to be leaving behind unused emergency slot.
; Writing to M0 from an SMRD instruction will hang the GPU.
-; CHECK-NOT: s_buffer_load_dword m0
-; CHECK: s_endpgm
+; GCN-NOT: s_buffer_load_dword m0
+; GCN: s_endpgm
; TOVGPR: ScratchSize: 4{{$}}
define amdgpu_ps void @main([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) {
@@ -104,104 +104,104 @@ main_body:
%j.i = extractelement <2 x i32> %arg6, i32 1
%i.f.i = bitcast i32 %i.i to float
%j.f.i = bitcast i32 %j.i to float
- %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg4) #1
- %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg4) #1
+ %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg4) #0
+ %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg4) #0
%i.i91 = extractelement <2 x i32> %arg6, i32 0
%j.i92 = extractelement <2 x i32> %arg6, i32 1
%i.f.i93 = bitcast i32 %i.i91 to float
%j.f.i94 = bitcast i32 %j.i92 to float
- %p1.i95 = call float @llvm.amdgcn.interp.p1(float %i.f.i93, i32 1, i32 0, i32 %arg4) #1
- %p2.i96 = call float @llvm.amdgcn.interp.p2(float %p1.i95, float %j.f.i94, i32 1, i32 0, i32 %arg4) #1
+ %p1.i95 = call float @llvm.amdgcn.interp.p1(float %i.f.i93, i32 1, i32 0, i32 %arg4) #0
+ %p2.i96 = call float @llvm.amdgcn.interp.p2(float %p1.i95, float %j.f.i94, i32 1, i32 0, i32 %arg4) #0
%i.i85 = extractelement <2 x i32> %arg6, i32 0
%j.i86 = extractelement <2 x i32> %arg6, i32 1
%i.f.i87 = bitcast i32 %i.i85 to float
%j.f.i88 = bitcast i32 %j.i86 to float
- %p1.i89 = call float @llvm.amdgcn.interp.p1(float %i.f.i87, i32 0, i32 1, i32 %arg4) #1
- %p2.i90 = call float @llvm.amdgcn.interp.p2(float %p1.i89, float %j.f.i88, i32 0, i32 1, i32 %arg4) #1
+ %p1.i89 = call float @llvm.amdgcn.interp.p1(float %i.f.i87, i32 0, i32 1, i32 %arg4) #0
+ %p2.i90 = call float @llvm.amdgcn.interp.p2(float %p1.i89, float %j.f.i88, i32 0, i32 1, i32 %arg4) #0
%i.i79 = extractelement <2 x i32> %arg6, i32 0
%j.i80 = extractelement <2 x i32> %arg6, i32 1
%i.f.i81 = bitcast i32 %i.i79 to float
%j.f.i82 = bitcast i32 %j.i80 to float
- %p1.i83 = call float @llvm.amdgcn.interp.p1(float %i.f.i81, i32 1, i32 1, i32 %arg4) #1
- %p2.i84 = call float @llvm.amdgcn.interp.p2(float %p1.i83, float %j.f.i82, i32 1, i32 1, i32 %arg4) #1
+ %p1.i83 = call float @llvm.amdgcn.interp.p1(float %i.f.i81, i32 1, i32 1, i32 %arg4) #0
+ %p2.i84 = call float @llvm.amdgcn.interp.p2(float %p1.i83, float %j.f.i82, i32 1, i32 1, i32 %arg4) #0
%i.i73 = extractelement <2 x i32> %arg6, i32 0
%j.i74 = extractelement <2 x i32> %arg6, i32 1
%i.f.i75 = bitcast i32 %i.i73 to float
%j.f.i76 = bitcast i32 %j.i74 to float
- %p1.i77 = call float @llvm.amdgcn.interp.p1(float %i.f.i75, i32 2, i32 1, i32 %arg4) #1
- %p2.i78 = call float @llvm.amdgcn.interp.p2(float %p1.i77, float %j.f.i76, i32 2, i32 1, i32 %arg4) #1
+ %p1.i77 = call float @llvm.amdgcn.interp.p1(float %i.f.i75, i32 2, i32 1, i32 %arg4) #0
+ %p2.i78 = call float @llvm.amdgcn.interp.p2(float %p1.i77, float %j.f.i76, i32 2, i32 1, i32 %arg4) #0
%i.i67 = extractelement <2 x i32> %arg6, i32 0
%j.i68 = extractelement <2 x i32> %arg6, i32 1
%i.f.i69 = bitcast i32 %i.i67 to float
%j.f.i70 = bitcast i32 %j.i68 to float
- %p1.i71 = call float @llvm.amdgcn.interp.p1(float %i.f.i69, i32 0, i32 2, i32 %arg4) #1
- %p2.i72 = call float @llvm.amdgcn.interp.p2(float %p1.i71, float %j.f.i70, i32 0, i32 2, i32 %arg4) #1
+ %p1.i71 = call float @llvm.amdgcn.interp.p1(float %i.f.i69, i32 0, i32 2, i32 %arg4) #0
+ %p2.i72 = call float @llvm.amdgcn.interp.p2(float %p1.i71, float %j.f.i70, i32 0, i32 2, i32 %arg4) #0
%i.i61 = extractelement <2 x i32> %arg6, i32 0
%j.i62 = extractelement <2 x i32> %arg6, i32 1
%i.f.i63 = bitcast i32 %i.i61 to float
%j.f.i64 = bitcast i32 %j.i62 to float
- %p1.i65 = call float @llvm.amdgcn.interp.p1(float %i.f.i63, i32 1, i32 2, i32 %arg4) #1
- %p2.i66 = call float @llvm.amdgcn.interp.p2(float %p1.i65, float %j.f.i64, i32 1, i32 2, i32 %arg4) #1
+ %p1.i65 = call float @llvm.amdgcn.interp.p1(float %i.f.i63, i32 1, i32 2, i32 %arg4) #0
+ %p2.i66 = call float @llvm.amdgcn.interp.p2(float %p1.i65, float %j.f.i64, i32 1, i32 2, i32 %arg4) #0
%i.i55 = extractelement <2 x i32> %arg6, i32 0
%j.i56 = extractelement <2 x i32> %arg6, i32 1
%i.f.i57 = bitcast i32 %i.i55 to float
%j.f.i58 = bitcast i32 %j.i56 to float
- %p1.i59 = call float @llvm.amdgcn.interp.p1(float %i.f.i57, i32 2, i32 2, i32 %arg4) #1
- %p2.i60 = call float @llvm.amdgcn.interp.p2(float %p1.i59, float %j.f.i58, i32 2, i32 2, i32 %arg4) #1
+ %p1.i59 = call float @llvm.amdgcn.interp.p1(float %i.f.i57, i32 2, i32 2, i32 %arg4) #0
+ %p2.i60 = call float @llvm.amdgcn.interp.p2(float %p1.i59, float %j.f.i58, i32 2, i32 2, i32 %arg4) #0
%i.i49 = extractelement <2 x i32> %arg6, i32 0
%j.i50 = extractelement <2 x i32> %arg6, i32 1
%i.f.i51 = bitcast i32 %i.i49 to float
%j.f.i52 = bitcast i32 %j.i50 to float
- %p1.i53 = call float @llvm.amdgcn.interp.p1(float %i.f.i51, i32 0, i32 3, i32 %arg4) #1
- %p2.i54 = call float @llvm.amdgcn.interp.p2(float %p1.i53, float %j.f.i52, i32 0, i32 3, i32 %arg4) #1
+ %p1.i53 = call float @llvm.amdgcn.interp.p1(float %i.f.i51, i32 0, i32 3, i32 %arg4) #0
+ %p2.i54 = call float @llvm.amdgcn.interp.p2(float %p1.i53, float %j.f.i52, i32 0, i32 3, i32 %arg4) #0
%i.i43 = extractelement <2 x i32> %arg6, i32 0
%j.i44 = extractelement <2 x i32> %arg6, i32 1
%i.f.i45 = bitcast i32 %i.i43 to float
%j.f.i46 = bitcast i32 %j.i44 to float
- %p1.i47 = call float @llvm.amdgcn.interp.p1(float %i.f.i45, i32 1, i32 3, i32 %arg4) #1
- %p2.i48 = call float @llvm.amdgcn.interp.p2(float %p1.i47, float %j.f.i46, i32 1, i32 3, i32 %arg4) #1
+ %p1.i47 = call float @llvm.amdgcn.interp.p1(float %i.f.i45, i32 1, i32 3, i32 %arg4) #0
+ %p2.i48 = call float @llvm.amdgcn.interp.p2(float %p1.i47, float %j.f.i46, i32 1, i32 3, i32 %arg4) #0
%i.i37 = extractelement <2 x i32> %arg6, i32 0
%j.i38 = extractelement <2 x i32> %arg6, i32 1
%i.f.i39 = bitcast i32 %i.i37 to float
%j.f.i40 = bitcast i32 %j.i38 to float
- %p1.i41 = call float @llvm.amdgcn.interp.p1(float %i.f.i39, i32 2, i32 3, i32 %arg4) #1
- %p2.i42 = call float @llvm.amdgcn.interp.p2(float %p1.i41, float %j.f.i40, i32 2, i32 3, i32 %arg4) #1
+ %p1.i41 = call float @llvm.amdgcn.interp.p1(float %i.f.i39, i32 2, i32 3, i32 %arg4) #0
+ %p2.i42 = call float @llvm.amdgcn.interp.p2(float %p1.i41, float %j.f.i40, i32 2, i32 3, i32 %arg4) #0
%i.i31 = extractelement <2 x i32> %arg6, i32 0
%j.i32 = extractelement <2 x i32> %arg6, i32 1
%i.f.i33 = bitcast i32 %i.i31 to float
%j.f.i34 = bitcast i32 %j.i32 to float
- %p1.i35 = call float @llvm.amdgcn.interp.p1(float %i.f.i33, i32 0, i32 4, i32 %arg4) #1
- %p2.i36 = call float @llvm.amdgcn.interp.p2(float %p1.i35, float %j.f.i34, i32 0, i32 4, i32 %arg4) #1
+ %p1.i35 = call float @llvm.amdgcn.interp.p1(float %i.f.i33, i32 0, i32 4, i32 %arg4) #0
+ %p2.i36 = call float @llvm.amdgcn.interp.p2(float %p1.i35, float %j.f.i34, i32 0, i32 4, i32 %arg4) #0
%i.i25 = extractelement <2 x i32> %arg6, i32 0
%j.i26 = extractelement <2 x i32> %arg6, i32 1
%i.f.i27 = bitcast i32 %i.i25 to float
%j.f.i28 = bitcast i32 %j.i26 to float
- %p1.i29 = call float @llvm.amdgcn.interp.p1(float %i.f.i27, i32 1, i32 4, i32 %arg4) #1
- %p2.i30 = call float @llvm.amdgcn.interp.p2(float %p1.i29, float %j.f.i28, i32 1, i32 4, i32 %arg4) #1
+ %p1.i29 = call float @llvm.amdgcn.interp.p1(float %i.f.i27, i32 1, i32 4, i32 %arg4) #0
+ %p2.i30 = call float @llvm.amdgcn.interp.p2(float %p1.i29, float %j.f.i28, i32 1, i32 4, i32 %arg4) #0
%i.i19 = extractelement <2 x i32> %arg6, i32 0
%j.i20 = extractelement <2 x i32> %arg6, i32 1
%i.f.i21 = bitcast i32 %i.i19 to float
%j.f.i22 = bitcast i32 %j.i20 to float
- %p1.i23 = call float @llvm.amdgcn.interp.p1(float %i.f.i21, i32 2, i32 4, i32 %arg4) #1
- %p2.i24 = call float @llvm.amdgcn.interp.p2(float %p1.i23, float %j.f.i22, i32 2, i32 4, i32 %arg4) #1
+ %p1.i23 = call float @llvm.amdgcn.interp.p1(float %i.f.i21, i32 2, i32 4, i32 %arg4) #0
+ %p2.i24 = call float @llvm.amdgcn.interp.p2(float %p1.i23, float %j.f.i22, i32 2, i32 4, i32 %arg4) #0
%i.i13 = extractelement <2 x i32> %arg6, i32 0
%j.i14 = extractelement <2 x i32> %arg6, i32 1
%i.f.i15 = bitcast i32 %i.i13 to float
%j.f.i16 = bitcast i32 %j.i14 to float
- %p1.i17 = call float @llvm.amdgcn.interp.p1(float %i.f.i15, i32 0, i32 5, i32 %arg4) #1
- %p2.i18 = call float @llvm.amdgcn.interp.p2(float %p1.i17, float %j.f.i16, i32 0, i32 5, i32 %arg4) #1
+ %p1.i17 = call float @llvm.amdgcn.interp.p1(float %i.f.i15, i32 0, i32 5, i32 %arg4) #0
+ %p2.i18 = call float @llvm.amdgcn.interp.p2(float %p1.i17, float %j.f.i16, i32 0, i32 5, i32 %arg4) #0
%i.i7 = extractelement <2 x i32> %arg6, i32 0
%j.i8 = extractelement <2 x i32> %arg6, i32 1
%i.f.i9 = bitcast i32 %i.i7 to float
%j.f.i10 = bitcast i32 %j.i8 to float
- %p1.i11 = call float @llvm.amdgcn.interp.p1(float %i.f.i9, i32 1, i32 5, i32 %arg4) #1
- %p2.i12 = call float @llvm.amdgcn.interp.p2(float %p1.i11, float %j.f.i10, i32 1, i32 5, i32 %arg4) #1
+ %p1.i11 = call float @llvm.amdgcn.interp.p1(float %i.f.i9, i32 1, i32 5, i32 %arg4) #0
+ %p2.i12 = call float @llvm.amdgcn.interp.p2(float %p1.i11, float %j.f.i10, i32 1, i32 5, i32 %arg4) #0
%i.i1 = extractelement <2 x i32> %arg6, i32 0
%j.i2 = extractelement <2 x i32> %arg6, i32 1
%i.f.i3 = bitcast i32 %i.i1 to float
%j.f.i4 = bitcast i32 %j.i2 to float
- %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 2, i32 5, i32 %arg4) #1
- %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 2, i32 5, i32 %arg4) #1
+ %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 2, i32 5, i32 %arg4) #0
+ %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 2, i32 5, i32 %arg4) #0
%mbcnt.lo.0 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
%tmp109 = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo.0)
%tmp110 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp109
@@ -590,7 +590,6 @@ IF67:
%tmp449 = insertelement <4 x float> %tmp448, float %tmp445, i32 1
%tmp450 = insertelement <4 x float> %tmp449, float %tmp447, i32 2
%tmp451 = insertelement <4 x float> %tmp450, float %tmp194, i32 3
-
%tmp451.x = extractelement <4 x float> %tmp451, i32 0
%tmp451.y = extractelement <4 x float> %tmp451, i32 1
%tmp451.z = extractelement <4 x float> %tmp451, i32 2
@@ -602,7 +601,6 @@ IF67:
%tmp452.1 = insertelement <4 x float> %tmp452.0, float %cubesc, i32 1
%tmp452.2 = insertelement <4 x float> %tmp452.1, float %cubema, i32 2
%tmp452 = insertelement <4 x float> %tmp452.2, float %cubeid, i32 3
-
%tmp453 = extractelement <4 x float> %tmp452, i32 0
%tmp454 = extractelement <4 x float> %tmp452, i32 1
%tmp455 = extractelement <4 x float> %tmp452, i32 2
@@ -770,8 +768,8 @@ ENDIF66:
br label %LOOP65
}
-; CHECK-LABEL: {{^}}main1:
-; CHECK: s_endpgm
+; GCN-LABEL: {{^}}main1:
+; GCN: s_endpgm
; TOVGPR: ScratchSize: 4{{$}}
define amdgpu_ps void @main1([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) {
main_body:
@@ -922,201 +920,199 @@ main_body:
%j.i = extractelement <2 x i32> %arg6, i32 1
%i.f.i = bitcast i32 %i.i to float
%j.f.i = bitcast i32 %j.i to float
- %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg4) #1
- %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg4) #1
+ %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg4) #0
+ %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg4) #0
%i.i181 = extractelement <2 x i32> %arg6, i32 0
%j.i182 = extractelement <2 x i32> %arg6, i32 1
%i.f.i183 = bitcast i32 %i.i181 to float
%j.f.i184 = bitcast i32 %j.i182 to float
- %p1.i185 = call float @llvm.amdgcn.interp.p1(float %i.f.i183, i32 1, i32 0, i32 %arg4) #1
- %p2.i186 = call float @llvm.amdgcn.interp.p2(float %p1.i185, float %j.f.i184, i32 1, i32 0, i32 %arg4) #1
+ %p1.i185 = call float @llvm.amdgcn.interp.p1(float %i.f.i183, i32 1, i32 0, i32 %arg4) #0
+ %p2.i186 = call float @llvm.amdgcn.interp.p2(float %p1.i185, float %j.f.i184, i32 1, i32 0, i32 %arg4) #0
%i.i175 = extractelement <2 x i32> %arg6, i32 0
%j.i176 = extractelement <2 x i32> %arg6, i32 1
%i.f.i177 = bitcast i32 %i.i175 to float
%j.f.i178 = bitcast i32 %j.i176 to float
- %p1.i179 = call float @llvm.amdgcn.interp.p1(float %i.f.i177, i32 2, i32 0, i32 %arg4) #1
- %p2.i180 = call float @llvm.amdgcn.interp.p2(float %p1.i179, float %j.f.i178, i32 2, i32 0, i32 %arg4) #1
+ %p1.i179 = call float @llvm.amdgcn.interp.p1(float %i.f.i177, i32 2, i32 0, i32 %arg4) #0
+ %p2.i180 = call float @llvm.amdgcn.interp.p2(float %p1.i179, float %j.f.i178, i32 2, i32 0, i32 %arg4) #0
%i.i169 = extractelement <2 x i32> %arg6, i32 0
%j.i170 = extractelement <2 x i32> %arg6, i32 1
%i.f.i171 = bitcast i32 %i.i169 to float
%j.f.i172 = bitcast i32 %j.i170 to float
- %p1.i173 = call float @llvm.amdgcn.interp.p1(float %i.f.i171, i32 3, i32 0, i32 %arg4) #1
- %p2.i174 = call float @llvm.amdgcn.interp.p2(float %p1.i173, float %j.f.i172, i32 3, i32 0, i32 %arg4) #1
+ %p1.i173 = call float @llvm.amdgcn.interp.p1(float %i.f.i171, i32 3, i32 0, i32 %arg4) #0
+ %p2.i174 = call float @llvm.amdgcn.interp.p2(float %p1.i173, float %j.f.i172, i32 3, i32 0, i32 %arg4) #0
%i.i163 = extractelement <2 x i32> %arg6, i32 0
%j.i164 = extractelement <2 x i32> %arg6, i32 1
%i.f.i165 = bitcast i32 %i.i163 to float
%j.f.i166 = bitcast i32 %j.i164 to float
- %p1.i167 = call float @llvm.amdgcn.interp.p1(float %i.f.i165, i32 0, i32 1, i32 %arg4) #1
- %p2.i168 = call float @llvm.amdgcn.interp.p2(float %p1.i167, float %j.f.i166, i32 0, i32 1, i32 %arg4) #1
+ %p1.i167 = call float @llvm.amdgcn.interp.p1(float %i.f.i165, i32 0, i32 1, i32 %arg4) #0
+ %p2.i168 = call float @llvm.amdgcn.interp.p2(float %p1.i167, float %j.f.i166, i32 0, i32 1, i32 %arg4) #0
%i.i157 = extractelement <2 x i32> %arg6, i32 0
%j.i158 = extractelement <2 x i32> %arg6, i32 1
%i.f.i159 = bitcast i32 %i.i157 to float
%j.f.i160 = bitcast i32 %j.i158 to float
- %p1.i161 = call float @llvm.amdgcn.interp.p1(float %i.f.i159, i32 1, i32 1, i32 %arg4) #1
- %p2.i162 = call float @llvm.amdgcn.interp.p2(float %p1.i161, float %j.f.i160, i32 1, i32 1, i32 %arg4) #1
+ %p1.i161 = call float @llvm.amdgcn.interp.p1(float %i.f.i159, i32 1, i32 1, i32 %arg4) #0
+ %p2.i162 = call float @llvm.amdgcn.interp.p2(float %p1.i161, float %j.f.i160, i32 1, i32 1, i32 %arg4) #0
%i.i151 = extractelement <2 x i32> %arg6, i32 0
%j.i152 = extractelement <2 x i32> %arg6, i32 1
%i.f.i153 = bitcast i32 %i.i151 to float
%j.f.i154 = bitcast i32 %j.i152 to float
- %p1.i155 = call float @llvm.amdgcn.interp.p1(float %i.f.i153, i32 2, i32 1, i32 %arg4) #1
- %p2.i156 = call float @llvm.amdgcn.interp.p2(float %p1.i155, float %j.f.i154, i32 2, i32 1, i32 %arg4) #1
+ %p1.i155 = call float @llvm.amdgcn.interp.p1(float %i.f.i153, i32 2, i32 1, i32 %arg4) #0
+ %p2.i156 = call float @llvm.amdgcn.interp.p2(float %p1.i155, float %j.f.i154, i32 2, i32 1, i32 %arg4) #0
%i.i145 = extractelement <2 x i32> %arg6, i32 0
%j.i146 = extractelement <2 x i32> %arg6, i32 1
%i.f.i147 = bitcast i32 %i.i145 to float
%j.f.i148 = bitcast i32 %j.i146 to float
- %p1.i149 = call float @llvm.amdgcn.interp.p1(float %i.f.i147, i32 3, i32 1, i32 %arg4) #1
- %p2.i150 = call float @llvm.amdgcn.interp.p2(float %p1.i149, float %j.f.i148, i32 3, i32 1, i32 %arg4) #1
+ %p1.i149 = call float @llvm.amdgcn.interp.p1(float %i.f.i147, i32 3, i32 1, i32 %arg4) #0
+ %p2.i150 = call float @llvm.amdgcn.interp.p2(float %p1.i149, float %j.f.i148, i32 3, i32 1, i32 %arg4) #0
%i.i139 = extractelement <2 x i32> %arg6, i32 0
%j.i140 = extractelement <2 x i32> %arg6, i32 1
%i.f.i141 = bitcast i32 %i.i139 to float
%j.f.i142 = bitcast i32 %j.i140 to float
- %p1.i143 = call float @llvm.amdgcn.interp.p1(float %i.f.i141, i32 0, i32 2, i32 %arg4) #1
- %p2.i144 = call float @llvm.amdgcn.interp.p2(float %p1.i143, float %j.f.i142, i32 0, i32 2, i32 %arg4) #1
+ %p1.i143 = call float @llvm.amdgcn.interp.p1(float %i.f.i141, i32 0, i32 2, i32 %arg4) #0
+ %p2.i144 = call float @llvm.amdgcn.interp.p2(float %p1.i143, float %j.f.i142, i32 0, i32 2, i32 %arg4) #0
%i.i133 = extractelement <2 x i32> %arg6, i32 0
%j.i134 = extractelement <2 x i32> %arg6, i32 1
%i.f.i135 = bitcast i32 %i.i133 to float
%j.f.i136 = bitcast i32 %j.i134 to float
- %p1.i137 = call float @llvm.amdgcn.interp.p1(float %i.f.i135, i32 1, i32 2, i32 %arg4) #1
- %p2.i138 = call float @llvm.amdgcn.interp.p2(float %p1.i137, float %j.f.i136, i32 1, i32 2, i32 %arg4) #1
+ %p1.i137 = call float @llvm.amdgcn.interp.p1(float %i.f.i135, i32 1, i32 2, i32 %arg4) #0
+ %p2.i138 = call float @llvm.amdgcn.interp.p2(float %p1.i137, float %j.f.i136, i32 1, i32 2, i32 %arg4) #0
%i.i127 = extractelement <2 x i32> %arg6, i32 0
%j.i128 = extractelement <2 x i32> %arg6, i32 1
%i.f.i129 = bitcast i32 %i.i127 to float
%j.f.i130 = bitcast i32 %j.i128 to float
- %p1.i131 = call float @llvm.amdgcn.interp.p1(float %i.f.i129, i32 2, i32 2, i32 %arg4) #1
- %p2.i132 = call float @llvm.amdgcn.interp.p2(float %p1.i131, float %j.f.i130, i32 2, i32 2, i32 %arg4) #1
+ %p1.i131 = call float @llvm.amdgcn.interp.p1(float %i.f.i129, i32 2, i32 2, i32 %arg4) #0
+ %p2.i132 = call float @llvm.amdgcn.interp.p2(float %p1.i131, float %j.f.i130, i32 2, i32 2, i32 %arg4) #0
%i.i121 = extractelement <2 x i32> %arg6, i32 0
%j.i122 = extractelement <2 x i32> %arg6, i32 1
%i.f.i123 = bitcast i32 %i.i121 to float
%j.f.i124 = bitcast i32 %j.i122 to float
- %p1.i125 = call float @llvm.amdgcn.interp.p1(float %i.f.i123, i32 3, i32 2, i32 %arg4) #1
- %p2.i126 = call float @llvm.amdgcn.interp.p2(float %p1.i125, float %j.f.i124, i32 3, i32 2, i32 %arg4) #1
+ %p1.i125 = call float @llvm.amdgcn.interp.p1(float %i.f.i123, i32 3, i32 2, i32 %arg4) #0
+ %p2.i126 = call float @llvm.amdgcn.interp.p2(float %p1.i125, float %j.f.i124, i32 3, i32 2, i32 %arg4) #0
%i.i115 = extractelement <2 x i32> %arg6, i32 0
%j.i116 = extractelement <2 x i32> %arg6, i32 1
%i.f.i117 = bitcast i32 %i.i115 to float
%j.f.i118 = bitcast i32 %j.i116 to float
- %p1.i119 = call float @llvm.amdgcn.interp.p1(float %i.f.i117, i32 0, i32 3, i32 %arg4) #1
- %p2.i120 = call float @llvm.amdgcn.interp.p2(float %p1.i119, float %j.f.i118, i32 0, i32 3, i32 %arg4) #1
+ %p1.i119 = call float @llvm.amdgcn.interp.p1(float %i.f.i117, i32 0, i32 3, i32 %arg4) #0
+ %p2.i120 = call float @llvm.amdgcn.interp.p2(float %p1.i119, float %j.f.i118, i32 0, i32 3, i32 %arg4) #0
%i.i109 = extractelement <2 x i32> %arg6, i32 0
%j.i110 = extractelement <2 x i32> %arg6, i32 1
%i.f.i111 = bitcast i32 %i.i109 to float
%j.f.i112 = bitcast i32 %j.i110 to float
- %p1.i113 = call float @llvm.amdgcn.interp.p1(float %i.f.i111, i32 1, i32 3, i32 %arg4) #1
- %p2.i114 = call float @llvm.amdgcn.interp.p2(float %p1.i113, float %j.f.i112, i32 1, i32 3, i32 %arg4) #1
+ %p1.i113 = call float @llvm.amdgcn.interp.p1(float %i.f.i111, i32 1, i32 3, i32 %arg4) #0
+ %p2.i114 = call float @llvm.amdgcn.interp.p2(float %p1.i113, float %j.f.i112, i32 1, i32 3, i32 %arg4) #0
%i.i103 = extractelement <2 x i32> %arg6, i32 0
%j.i104 = extractelement <2 x i32> %arg6, i32 1
%i.f.i105 = bitcast i32 %i.i103 to float
%j.f.i106 = bitcast i32 %j.i104 to float
- %p1.i107 = call float @llvm.amdgcn.interp.p1(float %i.f.i105, i32 2, i32 3, i32 %arg4) #1
- %p2.i108 = call float @llvm.amdgcn.interp.p2(float %p1.i107, float %j.f.i106, i32 2, i32 3, i32 %arg4) #1
+ %p1.i107 = call float @llvm.amdgcn.interp.p1(float %i.f.i105, i32 2, i32 3, i32 %arg4) #0
+ %p2.i108 = call float @llvm.amdgcn.interp.p2(float %p1.i107, float %j.f.i106, i32 2, i32 3, i32 %arg4) #0
%i.i97 = extractelement <2 x i32> %arg6, i32 0
%j.i98 = extractelement <2 x i32> %arg6, i32 1
%i.f.i99 = bitcast i32 %i.i97 to float
%j.f.i100 = bitcast i32 %j.i98 to float
- %p1.i101 = call float @llvm.amdgcn.interp.p1(float %i.f.i99, i32 3, i32 3, i32 %arg4) #1
- %p2.i102 = call float @llvm.amdgcn.interp.p2(float %p1.i101, float %j.f.i100, i32 3, i32 3, i32 %arg4) #1
+ %p1.i101 = call float @llvm.amdgcn.interp.p1(float %i.f.i99, i32 3, i32 3, i32 %arg4) #0
+ %p2.i102 = call float @llvm.amdgcn.interp.p2(float %p1.i101, float %j.f.i100, i32 3, i32 3, i32 %arg4) #0
%i.i91 = extractelement <2 x i32> %arg6, i32 0
%j.i92 = extractelement <2 x i32> %arg6, i32 1
%i.f.i93 = bitcast i32 %i.i91 to float
%j.f.i94 = bitcast i32 %j.i92 to float
- %p1.i95 = call float @llvm.amdgcn.interp.p1(float %i.f.i93, i32 0, i32 4, i32 %arg4) #1
- %p2.i96 = call float @llvm.amdgcn.interp.p2(float %p1.i95, float %j.f.i94, i32 0, i32 4, i32 %arg4) #1
+ %p1.i95 = call float @llvm.amdgcn.interp.p1(float %i.f.i93, i32 0, i32 4, i32 %arg4) #0
+ %p2.i96 = call float @llvm.amdgcn.interp.p2(float %p1.i95, float %j.f.i94, i32 0, i32 4, i32 %arg4) #0
%i.i85 = extractelement <2 x i32> %arg6, i32 0
%j.i86 = extractelement <2 x i32> %arg6, i32 1
%i.f.i87 = bitcast i32 %i.i85 to float
%j.f.i88 = bitcast i32 %j.i86 to float
- %p1.i89 = call float @llvm.amdgcn.interp.p1(float %i.f.i87, i32 1, i32 4, i32 %arg4) #1
- %p2.i90 = call float @llvm.amdgcn.interp.p2(float %p1.i89, float %j.f.i88, i32 1, i32 4, i32 %arg4) #1
+ %p1.i89 = call float @llvm.amdgcn.interp.p1(float %i.f.i87, i32 1, i32 4, i32 %arg4) #0
+ %p2.i90 = call float @llvm.amdgcn.interp.p2(float %p1.i89, float %j.f.i88, i32 1, i32 4, i32 %arg4) #0
%i.i79 = extractelement <2 x i32> %arg6, i32 0
%j.i80 = extractelement <2 x i32> %arg6, i32 1
%i.f.i81 = bitcast i32 %i.i79 to float
%j.f.i82 = bitcast i32 %j.i80 to float
- %p1.i83 = call float @llvm.amdgcn.interp.p1(float %i.f.i81, i32 2, i32 4, i32 %arg4) #1
- %p2.i84 = call float @llvm.amdgcn.interp.p2(float %p1.i83, float %j.f.i82, i32 2, i32 4, i32 %arg4) #1
+ %p1.i83 = call float @llvm.amdgcn.interp.p1(float %i.f.i81, i32 2, i32 4, i32 %arg4) #0
+ %p2.i84 = call float @llvm.amdgcn.interp.p2(float %p1.i83, float %j.f.i82, i32 2, i32 4, i32 %arg4) #0
%i.i73 = extractelement <2 x i32> %arg6, i32 0
%j.i74 = extractelement <2 x i32> %arg6, i32 1
%i.f.i75 = bitcast i32 %i.i73 to float
%j.f.i76 = bitcast i32 %j.i74 to float
- %p1.i77 = call float @llvm.amdgcn.interp.p1(float %i.f.i75, i32 3, i32 4, i32 %arg4) #1
- %p2.i78 = call float @llvm.amdgcn.interp.p2(float %p1.i77, float %j.f.i76, i32 3, i32 4, i32 %arg4) #1
+ %p1.i77 = call float @llvm.amdgcn.interp.p1(float %i.f.i75, i32 3, i32 4, i32 %arg4) #0
+ %p2.i78 = call float @llvm.amdgcn.interp.p2(float %p1.i77, float %j.f.i76, i32 3, i32 4, i32 %arg4) #0
%i.i67 = extractelement <2 x i32> %arg6, i32 0
%j.i68 = extractelement <2 x i32> %arg6, i32 1
%i.f.i69 = bitcast i32 %i.i67 to float
%j.f.i70 = bitcast i32 %j.i68 to float
- %p1.i71 = call float @llvm.amdgcn.interp.p1(float %i.f.i69, i32 0, i32 5, i32 %arg4) #1
- %p2.i72 = call float @llvm.amdgcn.interp.p2(float %p1.i71, float %j.f.i70, i32 0, i32 5, i32 %arg4) #1
+ %p1.i71 = call float @llvm.amdgcn.interp.p1(float %i.f.i69, i32 0, i32 5, i32 %arg4) #0
+ %p2.i72 = call float @llvm.amdgcn.interp.p2(float %p1.i71, float %j.f.i70, i32 0, i32 5, i32 %arg4) #0
%i.i61 = extractelement <2 x i32> %arg6, i32 0
%j.i62 = extractelement <2 x i32> %arg6, i32 1
%i.f.i63 = bitcast i32 %i.i61 to float
%j.f.i64 = bitcast i32 %j.i62 to float
- %p1.i65 = call float @llvm.amdgcn.interp.p1(float %i.f.i63, i32 1, i32 5, i32 %arg4) #1
- %p2.i66 = call float @llvm.amdgcn.interp.p2(float %p1.i65, float %j.f.i64, i32 1, i32 5, i32 %arg4) #1
+ %p1.i65 = call float @llvm.amdgcn.interp.p1(float %i.f.i63, i32 1, i32 5, i32 %arg4) #0
+ %p2.i66 = call float @llvm.amdgcn.interp.p2(float %p1.i65, float %j.f.i64, i32 1, i32 5, i32 %arg4) #0
%i.i55 = extractelement <2 x i32> %arg6, i32 0
%j.i56 = extractelement <2 x i32> %arg6, i32 1
%i.f.i57 = bitcast i32 %i.i55 to float
%j.f.i58 = bitcast i32 %j.i56 to float
- %p1.i59 = call float @llvm.amdgcn.interp.p1(float %i.f.i57, i32 2, i32 5, i32 %arg4) #1
- %p2.i60 = call float @llvm.amdgcn.interp.p2(float %p1.i59, float %j.f.i58, i32 2, i32 5, i32 %arg4) #1
+ %p1.i59 = call float @llvm.amdgcn.interp.p1(float %i.f.i57, i32 2, i32 5, i32 %arg4) #0
+ %p2.i60 = call float @llvm.amdgcn.interp.p2(float %p1.i59, float %j.f.i58, i32 2, i32 5, i32 %arg4) #0
%i.i49 = extractelement <2 x i32> %arg6, i32 0
%j.i50 = extractelement <2 x i32> %arg6, i32 1
%i.f.i51 = bitcast i32 %i.i49 to float
%j.f.i52 = bitcast i32 %j.i50 to float
- %p1.i53 = call float @llvm.amdgcn.interp.p1(float %i.f.i51, i32 3, i32 5, i32 %arg4) #1
- %p2.i54 = call float @llvm.amdgcn.interp.p2(float %p1.i53, float %j.f.i52, i32 3, i32 5, i32 %arg4) #1
+ %p1.i53 = call float @llvm.amdgcn.interp.p1(float %i.f.i51, i32 3, i32 5, i32 %arg4) #0
+ %p2.i54 = call float @llvm.amdgcn.interp.p2(float %p1.i53, float %j.f.i52, i32 3, i32 5, i32 %arg4) #0
%i.i43 = extractelement <2 x i32> %arg6, i32 0
%j.i44 = extractelement <2 x i32> %arg6, i32 1
%i.f.i45 = bitcast i32 %i.i43 to float
%j.f.i46 = bitcast i32 %j.i44 to float
- %p1.i47 = call float @llvm.amdgcn.interp.p1(float %i.f.i45, i32 0, i32 6, i32 %arg4) #1
- %p2.i48 = call float @llvm.amdgcn.interp.p2(float %p1.i47, float %j.f.i46, i32 0, i32 6, i32 %arg4) #1
+ %p1.i47 = call float @llvm.amdgcn.interp.p1(float %i.f.i45, i32 0, i32 6, i32 %arg4) #0
+ %p2.i48 = call float @llvm.amdgcn.interp.p2(float %p1.i47, float %j.f.i46, i32 0, i32 6, i32 %arg4) #0
%i.i37 = extractelement <2 x i32> %arg6, i32 0
%j.i38 = extractelement <2 x i32> %arg6, i32 1
%i.f.i39 = bitcast i32 %i.i37 to float
%j.f.i40 = bitcast i32 %j.i38 to float
- %p1.i41 = call float @llvm.amdgcn.interp.p1(float %i.f.i39, i32 1, i32 6, i32 %arg4) #1
- %p2.i42 = call float @llvm.amdgcn.interp.p2(float %p1.i41, float %j.f.i40, i32 1, i32 6, i32 %arg4) #1
+ %p1.i41 = call float @llvm.amdgcn.interp.p1(float %i.f.i39, i32 1, i32 6, i32 %arg4) #0
+ %p2.i42 = call float @llvm.amdgcn.interp.p2(float %p1.i41, float %j.f.i40, i32 1, i32 6, i32 %arg4) #0
%i.i31 = extractelement <2 x i32> %arg6, i32 0
%j.i32 = extractelement <2 x i32> %arg6, i32 1
%i.f.i33 = bitcast i32 %i.i31 to float
%j.f.i34 = bitcast i32 %j.i32 to float
- %p1.i35 = call float @llvm.amdgcn.interp.p1(float %i.f.i33, i32 2, i32 6, i32 %arg4) #1
- %p2.i36 = call float @llvm.amdgcn.interp.p2(float %p1.i35, float %j.f.i34, i32 2, i32 6, i32 %arg4) #1
+ %p1.i35 = call float @llvm.amdgcn.interp.p1(float %i.f.i33, i32 2, i32 6, i32 %arg4) #0
+ %p2.i36 = call float @llvm.amdgcn.interp.p2(float %p1.i35, float %j.f.i34, i32 2, i32 6, i32 %arg4) #0
%i.i25 = extractelement <2 x i32> %arg6, i32 0
%j.i26 = extractelement <2 x i32> %arg6, i32 1
%i.f.i27 = bitcast i32 %i.i25 to float
%j.f.i28 = bitcast i32 %j.i26 to float
- %p1.i29 = call float @llvm.amdgcn.interp.p1(float %i.f.i27, i32 3, i32 6, i32 %arg4) #1
- %p2.i30 = call float @llvm.amdgcn.interp.p2(float %p1.i29, float %j.f.i28, i32 3, i32 6, i32 %arg4) #1
+ %p1.i29 = call float @llvm.amdgcn.interp.p1(float %i.f.i27, i32 3, i32 6, i32 %arg4) #0
+ %p2.i30 = call float @llvm.amdgcn.interp.p2(float %p1.i29, float %j.f.i28, i32 3, i32 6, i32 %arg4) #0
%i.i19 = extractelement <2 x i32> %arg6, i32 0
%j.i20 = extractelement <2 x i32> %arg6, i32 1
%i.f.i21 = bitcast i32 %i.i19 to float
%j.f.i22 = bitcast i32 %j.i20 to float
- %p1.i23 = call float @llvm.amdgcn.interp.p1(float %i.f.i21, i32 0, i32 7, i32 %arg4) #1
- %p2.i24 = call float @llvm.amdgcn.interp.p2(float %p1.i23, float %j.f.i22, i32 0, i32 7, i32 %arg4) #1
+ %p1.i23 = call float @llvm.amdgcn.interp.p1(float %i.f.i21, i32 0, i32 7, i32 %arg4) #0
+ %p2.i24 = call float @llvm.amdgcn.interp.p2(float %p1.i23, float %j.f.i22, i32 0, i32 7, i32 %arg4) #0
%i.i13 = extractelement <2 x i32> %arg6, i32 0
%j.i14 = extractelement <2 x i32> %arg6, i32 1
%i.f.i15 = bitcast i32 %i.i13 to float
%j.f.i16 = bitcast i32 %j.i14 to float
- %p1.i17 = call float @llvm.amdgcn.interp.p1(float %i.f.i15, i32 1, i32 7, i32 %arg4) #1
- %p2.i18 = call float @llvm.amdgcn.interp.p2(float %p1.i17, float %j.f.i16, i32 1, i32 7, i32 %arg4) #1
+ %p1.i17 = call float @llvm.amdgcn.interp.p1(float %i.f.i15, i32 1, i32 7, i32 %arg4) #0
+ %p2.i18 = call float @llvm.amdgcn.interp.p2(float %p1.i17, float %j.f.i16, i32 1, i32 7, i32 %arg4) #0
%i.i7 = extractelement <2 x i32> %arg6, i32 0
%j.i8 = extractelement <2 x i32> %arg6, i32 1
%i.f.i9 = bitcast i32 %i.i7 to float
%j.f.i10 = bitcast i32 %j.i8 to float
- %p1.i11 = call float @llvm.amdgcn.interp.p1(float %i.f.i9, i32 2, i32 7, i32 %arg4) #1
- %p2.i12 = call float @llvm.amdgcn.interp.p2(float %p1.i11, float %j.f.i10, i32 2, i32 7, i32 %arg4) #1
+ %p1.i11 = call float @llvm.amdgcn.interp.p1(float %i.f.i9, i32 2, i32 7, i32 %arg4) #0
+ %p2.i12 = call float @llvm.amdgcn.interp.p2(float %p1.i11, float %j.f.i10, i32 2, i32 7, i32 %arg4) #0
%i.i1 = extractelement <2 x i32> %arg6, i32 0
%j.i2 = extractelement <2 x i32> %arg6, i32 1
%i.f.i3 = bitcast i32 %i.i1 to float
%j.f.i4 = bitcast i32 %j.i2 to float
- %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 3, i32 7, i32 %arg4) #1
- %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 3, i32 7, i32 %arg4) #1
+ %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 3, i32 7, i32 %arg4) #0
+ %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 3, i32 7, i32 %arg4) #0
%tmp195 = fmul float %arg14, %tmp123
%tmp196 = fadd float %tmp195, %tmp124
- %tmp197 = call float @llvm.AMDGPU.clamp.f32(float %tmp162, float 0.000000e+00, float 1.000000e+00)
- %tmp198 = call float @llvm.AMDGPU.clamp.f32(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
- %tmp199 = call float @llvm.AMDGPU.clamp.f32(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
- %tmp200 = call float @llvm.AMDGPU.clamp.f32(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
- %tmp201 = bitcast float %tmp197 to i32
+ %max.0.i = call float @llvm.maxnum.f32(float %tmp162, float 0.000000e+00)
+ %clamp.i = call float @llvm.minnum.f32(float %max.0.i, float 1.000000e+00)
+ %tmp201 = bitcast float %clamp.i to i32
%tmp202 = icmp ne i32 %tmp201, 0
%. = select i1 %tmp202, float -1.000000e+00, float 1.000000e+00
%tmp203 = fsub float -0.000000e+00, %p2.i
@@ -1171,19 +1167,21 @@ main_body:
%tmp245 = fadd float %tmp244, %tmp243
%tmp246 = fmul float %tmp217, %p2.i24
%tmp247 = fadd float %tmp245, %tmp246
- %tmp248 = call float @llvm.AMDGPU.clamp.f32(float %tmp247, float 0.000000e+00, float 1.000000e+00)
+ %max.0.i19 = call float @llvm.maxnum.f32(float %tmp247, float 0.000000e+00)
+ %clamp.i20 = call float @llvm.minnum.f32(float %max.0.i19, float 1.000000e+00)
%tmp249 = fmul float %tmp213, 0x3F5A36E2E0000000
- %tmp250 = call float @llvm.AMDGPU.clamp.f32(float %tmp249, float 0.000000e+00, float 1.000000e+00)
- %tmp251 = fsub float -0.000000e+00, %tmp250
+ %max.0.i17 = call float @llvm.maxnum.f32(float %tmp249, float 0.000000e+00)
+ %clamp.i18 = call float @llvm.minnum.f32(float %max.0.i17, float 1.000000e+00)
+ %tmp251 = fsub float -0.000000e+00, %clamp.i18
%tmp252 = fadd float 1.000000e+00, %tmp251
- %tmp253 = call float @llvm.pow.f32(float %tmp248, float 2.500000e-01)
+ %tmp253 = call float @llvm.pow.f32(float %clamp.i20, float 2.500000e-01)
%tmp254 = fmul float %tmp38, %tmp253
%tmp255 = fmul float %tmp237, %tmp254
%tmp256 = fmul float %tmp242, %tmp254
%tmp257 = fmul float %tmp255, %tmp229
%tmp258 = fmul float %tmp256, %tmp229
- %tmp259 = fadd float %tmp248, 0x3EE4F8B580000000
- %tmp260 = fsub float -0.000000e+00, %tmp248
+ %tmp259 = fadd float %clamp.i20, 0x3EE4F8B580000000
+ %tmp260 = fsub float -0.000000e+00, %clamp.i20
%tmp261 = fadd float 1.000000e+00, %tmp260
%tmp262 = fmul float 1.200000e+01, %tmp261
%tmp263 = fadd float %tmp262, 4.000000e+00
@@ -1383,10 +1381,11 @@ IF189:
%tmp426 = fadd float %tmp424, %tmp425
%tmp427 = fsub float -0.000000e+00, %tmp426
%tmp428 = fadd float 0x3FF00068E0000000, %tmp427
- %tmp429 = call float @llvm.AMDGPU.clamp.f32(float %tmp428, float 0.000000e+00, float 1.000000e+00)
- %tmp430 = call float @llvm.amdgcn.rsq.f32(float %tmp429)
- %tmp431 = fmul float %tmp430, %tmp429
- %tmp432 = fsub float -0.000000e+00, %tmp429
+ %max.0.i15 = call float @llvm.maxnum.f32(float %tmp428, float 0.000000e+00)
+ %clamp.i16 = call float @llvm.minnum.f32(float %max.0.i15, float 1.000000e+00)
+ %tmp430 = call float @llvm.amdgcn.rsq.f32(float %clamp.i16)
+ %tmp431 = fmul float %tmp430, %clamp.i16
+ %tmp432 = fsub float -0.000000e+00, %clamp.i16
%cmp = fcmp ogt float 0.000000e+00, %tmp432
%tmp433 = select i1 %cmp, float %tmp431, float 0.000000e+00
%tmp434 = fmul float %p2.i72, %tmp421
@@ -1503,10 +1502,11 @@ ENDIF197:
%tmp534 = fadd float %tmp533, %tmp532
%tmp535 = fmul float %temp14.0, %tmp531
%tmp536 = fadd float %tmp534, %tmp535
- %tmp537 = call float @llvm.AMDGPU.clamp.f32(float %tmp536, float 0.000000e+00, float 1.000000e+00)
- %tmp538 = fmul float %tmp364, %tmp537
- %tmp539 = fmul float %tmp365, %tmp537
- %tmp540 = fmul float %tmp366, %tmp537
+ %max.0.i13 = call float @llvm.maxnum.f32(float %tmp536, float 0.000000e+00)
+ %clamp.i14 = call float @llvm.minnum.f32(float %max.0.i13, float 1.000000e+00)
+ %tmp538 = fmul float %tmp364, %clamp.i14
+ %tmp539 = fmul float %tmp365, %clamp.i14
+ %tmp540 = fmul float %tmp366, %clamp.i14
%tmp541 = fmul float %tmp538, %tmp68
%tmp542 = fmul float %tmp539, %tmp69
%tmp543 = fmul float %tmp540, %tmp70
@@ -1650,7 +1650,8 @@ ENDIF209:
%tmp649 = fadd float %temp80.0, -1.000000e+00
%tmp650 = fmul float %tmp649, %tmp76
%tmp651 = fadd float %tmp650, 1.000000e+00
- %tmp652 = call float @llvm.AMDGPU.clamp.f32(float %tmp651, float 0.000000e+00, float 1.000000e+00)
+ %max.0.i11 = call float @llvm.maxnum.f32(float %tmp651, float 0.000000e+00)
+ %clamp.i12 = call float @llvm.minnum.f32(float %max.0.i11, float 1.000000e+00)
%tmp653 = bitcast float %tmp642 to i32
%tmp654 = bitcast float %tmp644 to i32
%tmp655 = bitcast float 0.000000e+00 to i32
@@ -1686,11 +1687,13 @@ ENDIF209:
%tmp684 = fadd float %tmp683, %temp89.0
%tmp685 = fmul float %tmp640, %temp90.0
%tmp686 = fadd float %tmp685, %temp91.0
- %tmp687 = call float @llvm.AMDGPU.clamp.f32(float %tmp684, float 0.000000e+00, float 1.000000e+00)
- %tmp688 = call float @llvm.AMDGPU.clamp.f32(float %tmp686, float 0.000000e+00, float 1.000000e+00)
- %tmp689 = fsub float -0.000000e+00, %tmp687
+ %max.0.i9 = call float @llvm.maxnum.f32(float %tmp684, float 0.000000e+00)
+ %clamp.i10 = call float @llvm.minnum.f32(float %max.0.i9, float 1.000000e+00)
+ %max.0.i7 = call float @llvm.maxnum.f32(float %tmp686, float 0.000000e+00)
+ %clamp.i8 = call float @llvm.minnum.f32(float %max.0.i7, float 1.000000e+00)
+ %tmp689 = fsub float -0.000000e+00, %clamp.i10
%tmp690 = fadd float %tmp661, %tmp689
- %tmp691 = fsub float -0.000000e+00, %tmp688
+ %tmp691 = fsub float -0.000000e+00, %clamp.i8
%tmp692 = fadd float %tmp671, %tmp691
%tmp693 = fmul float %tmp661, %tmp661
%tmp694 = fmul float %tmp671, %tmp671
@@ -1722,16 +1725,17 @@ ENDIF209:
%tmp719 = bitcast float %tmp718 to i32
%tmp720 = icmp ne i32 %tmp719, 0
%temp28.0 = select i1 %tmp720, float 1.000000e+00, float %tmp710
- %one.sub.a.i25 = fsub float 1.000000e+00, %tmp652
+ %one.sub.a.i25 = fsub float 1.000000e+00, %clamp.i12
%one.sub.ac.i26 = fmul float %one.sub.a.i25, %.229
%mul.i27 = fmul float %temp28.0, %.229
%result.i28 = fadd float %mul.i27, %one.sub.ac.i26
%tmp721 = call float @llvm.pow.f32(float %result.i28, float %tmp75)
%tmp722 = fmul float %tmp721, %tmp78
%tmp723 = fadd float %tmp722, %tmp79
- %tmp724 = call float @llvm.AMDGPU.clamp.f32(float %tmp723, float 0.000000e+00, float 1.000000e+00)
- %tmp725 = fmul float %tmp724, %tmp724
- %tmp726 = fmul float 2.000000e+00, %tmp724
+ %max.0.i5 = call float @llvm.maxnum.f32(float %tmp723, float 0.000000e+00)
+ %clamp.i6 = call float @llvm.minnum.f32(float %max.0.i5, float 1.000000e+00)
+ %tmp725 = fmul float %clamp.i6, %clamp.i6
+ %tmp726 = fmul float 2.000000e+00, %clamp.i6
%tmp727 = fsub float -0.000000e+00, %tmp726
%tmp728 = fadd float 3.000000e+00, %tmp727
%tmp729 = fmul float %tmp725, %tmp728
@@ -1769,8 +1773,9 @@ ENDIF209:
%tmp751 = fmul float %tmp750, %tmp750
%tmp752 = fmul float %tmp751, %tmp49
%tmp753 = fadd float %tmp752, %tmp50
- %tmp754 = call float @llvm.AMDGPU.clamp.f32(float %tmp753, float 0.000000e+00, float 1.000000e+00)
- %tmp755 = fsub float -0.000000e+00, %tmp754
+ %max.0.i3 = call float @llvm.maxnum.f32(float %tmp753, float 0.000000e+00)
+ %clamp.i4 = call float @llvm.minnum.f32(float %max.0.i3, float 1.000000e+00)
+ %tmp755 = fsub float -0.000000e+00, %clamp.i4
%tmp756 = fadd float 1.000000e+00, %tmp755
%tmp757 = fmul float %tmp32, %tmp756
%tmp758 = fmul float %tmp32, %tmp756
@@ -1806,10 +1811,11 @@ ENDIF209:
%tmp772 = select i1 %tmp771, float 6.550400e+04, float %tmp766
%tmp773 = fmul float %result.i2, %tmp51
%tmp774 = fadd float %tmp773, %tmp52
- %tmp775 = call float @llvm.AMDGPU.clamp.f32(float %tmp774, float 0.000000e+00, float 1.000000e+00)
+ %max.0.i1 = call float @llvm.maxnum.f32(float %tmp774, float 0.000000e+00)
+ %clamp.i2 = call float @llvm.minnum.f32(float %max.0.i1, float 1.000000e+00)
%tmp776 = call i32 @llvm.SI.packf16(float %tmp768, float %tmp770)
%tmp777 = bitcast i32 %tmp776 to float
- %tmp778 = call i32 @llvm.SI.packf16(float %tmp772, float %tmp775)
+ %tmp778 = call i32 @llvm.SI.packf16(float %tmp772, float %clamp.i2)
%tmp779 = bitcast i32 %tmp778 to float
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp777, float %tmp779, float %tmp777, float %tmp779)
ret void
@@ -1827,63 +1833,31 @@ ELSE214:
br label %ENDIF209
}
-; Function Attrs: nounwind readnone
-declare float @llvm.AMDGPU.clamp.f32(float, float, float) #0
-
-; Function Attrs: nounwind readnone
-declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0
-
-; Function Attrs: nounwind readnone
-declare <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0
-
-; Function Attrs: nounwind readnone
-declare float @llvm.exp2.f32(float) #0
-
-; Function Attrs: nounwind readnone
-declare float @llvm.SI.load.const(<16 x i8>, i32) #0
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0
-
-; Function Attrs: nounwind readnone
-declare float @llvm.ceil.f32(float) #0
-
-; Function Attrs: nounwind readnone
-declare float @llvm.amdgcn.rsq.f32(float) #0
-
-; Function Attrs: nounwind readnone
-declare <4 x float> @llvm.SI.image.sample.d.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0
-
-; Function Attrs: nounwind readnone
-declare float @llvm.fabs.f32(float) #0
-
-; Function Attrs: nounwind readnone
-declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0
-
-; Function Attrs: nounwind readnone
-declare float @llvm.pow.f32(float, float) #0
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.SI.packf16(float, float) #0
-
+declare float @llvm.exp2.f32(float) #1
+declare float @llvm.ceil.f32(float) #1
+declare float @llvm.amdgcn.rsq.f32(float) #1
+declare float @llvm.fabs.f32(float) #1
+declare float @llvm.pow.f32(float, float) #1
+declare float @llvm.minnum.f32(float, float) #1
+declare float @llvm.maxnum.f32(float, float) #1
+declare float @llvm.amdgcn.cubeid(float, float, float) #1
+declare float @llvm.amdgcn.cubesc(float, float, float) #1
+declare float @llvm.amdgcn.cubetc(float, float, float) #1
+declare float @llvm.amdgcn.cubema(float, float, float) #1
+declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
+declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
+declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
+declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1
+declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
+declare <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
+declare <4 x float> @llvm.SI.image.sample.d.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
+declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
+declare float @llvm.SI.load.const(<16 x i8>, i32) #1
+declare i32 @llvm.SI.packf16(float, float) #1
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
-; Function Attrs: nounwind readnone
-declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #0
-
-; Function Attrs: nounwind readnone
-declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #0
-
-declare float @llvm.amdgcn.cubeid(float, float, float) #0
-declare float @llvm.amdgcn.cubesc(float, float, float) #0
-declare float @llvm.amdgcn.cubetc(float, float, float) #0
-declare float @llvm.amdgcn.cubema(float, float, float) #0
-
-attributes #0 = { nounwind readnone }
-attributes #1 = { nounwind }
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
!0 = !{!1, !1, i64 0, i32 1}
!1 = !{!"const", !2}
Modified: llvm/trunk/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/unigine-liveness-crash.ll?rev=295789&r1=295788&r2=295789&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/unigine-liveness-crash.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/unigine-liveness-crash.ll Tue Feb 21 17:46:04 2017
@@ -75,8 +75,9 @@ IF26:
ENDIF25: ; preds = %IF29, %main_body
%.4 = phi float [ %tmp84, %IF29 ], [ %tmp68, %main_body ]
%tmp73 = fadd float %.4, undef
- %tmp74 = call float @llvm.AMDGPU.clamp.(float %tmp73, float 0.000000e+00, float 1.000000e+00)
- %tmp75 = fmul float undef, %tmp74
+ %max.0.i = call float @llvm.maxnum.f32(float %tmp73, float 0.000000e+00)
+ %clamp.i = call float @llvm.minnum.f32(float %max.0.i, float 1.000000e+00)
+ %tmp75 = fmul float undef, %clamp.i
%tmp76 = fmul float %tmp75, undef
%tmp77 = fadd float %tmp76, undef
%tmp78 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, float %tmp77, 11
@@ -105,9 +106,6 @@ ENDIF28:
}
; Function Attrs: nounwind readnone
-declare float @llvm.AMDGPU.clamp.(float, float, float) #1
-
-; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
; Function Attrs: nounwind readnone
@@ -122,6 +120,12 @@ declare float @llvm.amdgcn.interp.p1(flo
; Function Attrs: nounwind readnone
declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
-attributes #0 = { "InitialPSInputAddr"="36983" "target-cpu"="tonga" }
+; Function Attrs: nounwind readnone
+declare float @llvm.minnum.f32(float, float) #1
+
+; Function Attrs: nounwind readnone
+declare float @llvm.maxnum.f32(float, float) #1
+
+attributes #0 = { nounwind "InitialPSInputAddr"="36983" "target-cpu"="tonga" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind }
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